Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 722 of 994
REJ09B0452-0200
21.4.6 SPI Flash Memory Write Operation Mode
The write operation to the SPI flash memory in the LPC/FW memory write cycles can be
classified into the following four operation modes, depending or the state of FLDCT and
FLWAIT.
Table 21.7 SPI Flash Memory Write Operation in LPC/FW Memory Write Cycles
Operation
Mode FLDCT FLWAIT Selected Register Operation
Mode 1 0 0 FSIWBUSY ← 1
FSIWI ← 1
Control the write operation to the SPI
flash memory by the EC CPU. No wait
cycle is inserted to the LPC bus. Confirm
by FSIWBUSY whether or not a write
transfer has been completed.
Mode 2 0 1 FSIWBUSY ← 1
FSIWI ← 1
Control the write operation to the SPI
flash memory by the EC CPU. Wait
cycles are inserted to the LPC bus.
Provision of wait cycles can be canceled
by clearing FSIWBUSY.
Mode 3 1 0 LFBUSY ← 1
(Automatically
cleared)
Control the write operation to the SPI
flash memory by the FSI. No wait cycle is
inserted to the LPC bus. Confirm by
LFBUSY whether or not a write transfer
has been completed.
Mode 4 1 1 LFBUSY ← 1
(Automatically
cleared)
Control the write operation to the SPI
flash memory by the FSI. Wait cycles are
inserted to the LPC bus. Provision of wait
cycles can be canceled by clearing
LFBUSY.