To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual 16 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Rev. 2.00 Sep.
How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers.
2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name".
3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. (1) [Table of Bits] Bit (2) (3) (4) (5) Bit Name − − Initial Value R/W Description 0 0 R R Reserved These bits are always read as 0. 13 to 11 ASID2 to ASID0 All 0 R/W Address Identifier These bits enable or disable the pin function.
4. Description of Abbreviations The abbreviations used in this manual are listed below.
Main Revisions for This Edition Item Page 2.4.3 Extended Control 39 Register (EXR) Revision (See Manual for Details) Table amended Bit Bit Name Initial Value R/W Description 7 T 0 R/W Trace Bit 2 I2 1 R/W Interrupt Request Mask Bits 2 to 0 1 I1 1 R/W These bits have no effect on the operation of the MCU. 0 I0 1 R/W This bit has no effect on the operation of the MCU. 2.4.
Item Page Revision (See Manual for Details) 8.4.2 Pulse Division Mode 215 Figure amended Figure 8.8 Example of Additional Pulse Timing (Upper 4 Bits in PWMREG = B'1000) No pulse added Resolution width Pulse added Additional pulse Figure 8.9 Example of WMU Setting 216 Figure amended 1 conversion period PWMREG setting example Duty cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 H'7F 127/256 H'80 128/256 H'81 129/256 H'82 130/256 : Position of additional pulse 10.3.
Item Page Revision (See Manual for Details) 15.1 Features 403 Figure amended Figure 15.1 Block Diagram of SCI RxD RSR TxD SCK 15.3 Register Descriptions 406 Channel Table 15.2 Register Configuration 15.4.
Item Page Revision (See Manual for Details) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) 444 Figure amended No TEND = 1 Figure 15.17 Sample Serial Transmission Flowchart Yes Clear TE bit in SCR to 0 [4] End transmission 15.6.4 Serial Data Reception (Clocked Synchronous Mode) 446 Figure amended No Figure 15.
Item Page Revision (See Manual for Details) 17.3.8 FIFO Control Register (FFCR) 502 Table amended Bit Bit Name Initial Value R/W 2 XMITFRST 0 W Description Transmit FIFO Reset The transmit FIFO data is cleared when 1 is written. However, FTSR data is not cleared. This bit is automatically cleared. 1 RCVRFRST 0 W Receive FIFO Reset The receive FIFO data is cleared when 1 is written. However, FRSR data is not cleared. This bit is automatically cleared. 17.4.
Item Page Revision (See Manual for Details) 18.4.5 Slave Receive Operation 573 Figure amended Figure 18.15 Example of Slave Receive Mode Operation Timing (2) (MLS = 0) ICDRR [8] IRIC clear [10] ICDR read (Data (n-1)) [9] Set ACKB=1 User processing 19.3.2 Keyboard Buffer 593 Control Register 2 (KBCR2) Data (n-1) Data (n-2) Table amended Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 R/W Reserved These bits are always read as 1. The initial value should not be changed. 19.3.
Item Page Revision (See Manual for Details) 20.1 Features 616 Figure amended Figure 20.1 Block Diagram of LPC IDR4 TWR0MW IDR3 IDR2 TWR1 to TWR15 20.3 Register Descriptions 619 Table 20.2 Register Configuration 20.3.
Item Page Revision (See Manual for Details) 20.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) 638 Description amended When the host and slave begin a write, after the respective registers of TWR0 have been written to, arbitration for simultaneous access is performed by checking the status flags whether or not those writes were valid. When the host has access rights, TWR0MW is selected in TWR0 and the state of TWR0MW is returned when the host reads TWR0SW.
Item Page Revision (See Manual for Details) 22.4.3 Input Sampling and A/D Conversion Time 738 Table amended Table 22.5 A/D Conversion Time (Scan Mode) 22.7.2 Permissible Signal Source Impedance 741 CKS1 CKS0 1 0 1 1 Figure amended This LSI Sensor output impedance Up to 5 kΩ Figure 22.5 Example of Analog Input Circuit A/D converter equivalent circuit 10 kΩ Sensor input Cin = 10 pF Low-pass filter C Up to 0.1 µF 22.7.6 Notes on Noise Countermeasures 743 Figure 22.
Item Page Revision (See Manual for Details) 24.1 Features 749 Description amended • Two flash-memory MATs according to LSI initiation mode. The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs). The mode setting at initiation determines which memory MAT is initiated first. The MAT can be switched by using the bank-switching method after initiation.
Item Page Revision (See Manual for Details) 24.5 Programming/Erasing Interface 754 Description amended 24.7.1 Programming/Erasing Interface Registers 763 The procedure program for user program mode/user boot mode is made by the user. Figure 24.5 shows the procedure for creating the procedure program. For details, see section 24.8.2, User Program Mode, section 24.8.3, User Boot Mode.
Item Page Revision (See Manual for Details) 24.8.4 Storable Areas for On-Chip Program and Program Data 795 Table amended Table 24.11 Usable Area for Erasure in User Program Mode Table 24.
Item Page 24.12 Standard Serial 803 Communication Interface Specifications for Boot Mode Revision (See Manual for Details) Figure amended Operations for erasing user MATs and user boot MATs Figure 24.18 Boot Program States Programming/ erasing wait Programming (3) Inquiry and Selection 811 States (f) Operating Clock Frequency Inquiry Description amended • Minimum value of operating clock frequency (two bytes): The minimum value of the divided clock frequency.
Item Page Revision (See Manual for Details) 27.1 Register Addresses (Address Order) 863 Table amended 28.2 DC Characteristics 958 Table 28.2 DC Characteristics (1) Register Name Abbreviation Number of bits Address Module Data Width Access States A/D control/status register ADCSR 8 H'FC10 A/D converter 8 2 A/D control register ADCR 8 H'FC11 A/D converter 8 2 Figure amended Test Item Input high voltage Symbol Min. Typ. Max. Unit VI H VCC × 0.9 — VCC + 0.
Contents Section 1 Overview..................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 1.1.1 Applications .............................................................................................................. 1 1.1.2 Overview of Functions...................................................................
2.8 2.9 2.7.3 Register Indirect with Displacement⎯@(d:16, ERn) or @(d:32, ERn)................. 58 2.7.4 Register Indirect with Post-Increment or Pre-Decrement⎯@ERn+ or @-ERn..... 58 2.7.5 Absolute Address⎯@aa:8, @aa:16, @aa:24, or @aa:32....................................... 58 2.7.6 Immediate⎯#xx:8, #xx:16, or #xx:32.................................................................... 59 2.7.7 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC)....................................... 59 2.7.
5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.4 5.5 5.6 5.7 5.8 Address Break Control Register (ABRKCR) ......................................................... 91 Break Address Registers A to C (BARA to BARC) ............................................... 92 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) ................... 93 IRQ Enable Registers (IER16, IER) ....................................................................... 96 IRQ Status Registers (ISR16, ISR) ..........................
Section 7 I/O Ports...............................................................................................135 7.1 7.2 7.3 Register Descriptions ......................................................................................................... 143 7.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to J) ............... 144 7.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9).......................................................... 145 7.1.
Section 8 8-Bit PWM Timer (PWMU)................................................................197 8.1 8.2 8.3 8.4 8.5 Features.............................................................................................................................. 197 Input/Output Pins ............................................................................................................... 199 Register Descriptions ..............................................................................................
10.4 10.5 10.6 10.7 10.8 10.3.6 Timer Counter (TCNT)......................................................................................... 263 10.3.7 Timer General Register (TGR) ............................................................................. 263 10.3.8 Timer Start Register (TSTR) ................................................................................ 263 10.3.9 Timer Synchro Register (TSYR) ..........................................................................
11.3.3 TCM Cycle Lower Limit Register (TCMMINCM) .............................................. 310 11.3.4 TCM Input Capture Register (TCMICR).............................................................. 310 11.3.5 TCM Input Capture Buffer Register (TCMICRF) ................................................ 310 11.3.6 TCM Status Register (TCMCSR) ......................................................................... 311 11.3.7 TCM Control Register (TCMCR)..................................................
12.6 Usage Notes ....................................................................................................................... 351 12.6.1 Conflict between TDPCNT Write and Count-Up Operation ................................ 351 12.6.2 Conflict between TDPPDMX Write and Compare Match.................................... 351 12.6.3 Conflict between Input Capture and TDPICR Read ............................................. 352 12.6.
13.7.3 Input Capture Operation ....................................................................................... 382 13.8 Interrupt Sources................................................................................................................ 384 13.9 Usage Notes ....................................................................................................................... 385 13.9.1 Conflict between TCNT Write and Counter Clear................................................ 385 13.
15.4 15.5 15.6 15.7 15.8 15.9 15.3.9 Bit Rate Register (BRR) ....................................................................................... 419 Operation in Asynchronous Mode ..................................................................................... 424 15.4.1 Data Transfer Format............................................................................................ 425 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode...............................
15.9.8 Note on Writing to Registers in Transmission, Reception, and Simultaneous Transmission and Reception .......................................................... 467 Section 16 CIR Interface......................................................................................469 16.1 Features.............................................................................................................................. 469 16.2 Input Pins ..................................................................
17.3.7 Interrupt Identification Register (FIIR)................................................................. 500 17.3.8 FIFO Control Register (FFCR)............................................................................. 502 17.3.9 Line Control Register (FLCR) .............................................................................. 503 17.3.10 Modem Control Register (FMCR)........................................................................ 504 17.3.11 Line Status Register (FLSR)..........
18.4.9 Initialization of Internal State ............................................................................... 579 18.5 Interrupt Sources................................................................................................................ 581 18.6 Usage Notes ....................................................................................................................... 582 18.6.1 Module Stop Mode Setting ............................................................................
20.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 630 20.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L)................ 631 20.3.6 LPC Channel 2 Address Registers H and L (LADR2H and LADR2L)................ 632 20.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 634 20.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 636 20.3.9 Input Data Registers 1 to 4 (IDR1 to IDR4) ..
21.4 21.5 21.6 21.7 21.3.6 FSI Program Instruction Register (FSIPPINS) ..................................................... 691 21.3.7 FSI Status Register (FSISTR) ............................................................................... 691 21.3.8 FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7)............................... 693 21.3.9 FSI Receive Data Register (FSIRDR)................................................................... 693 21.3.
22.5 Interrupt Source ................................................................................................................. 739 22.6 A/D Conversion Accuracy Definitions .............................................................................. 739 22.7 Usage Notes ....................................................................................................................... 741 22.7.1 Module Stop Mode Setting ...........................................................................
25.2 25.3 25.4 25.5 25.6 25.1.1 Connecting Crystal Resonator .............................................................................. 834 25.1.2 External Clock Input Method................................................................................ 835 Duty Correction Circuit ..................................................................................................... 838 Subclock Input Circuit ...............................................................................................
28.4 A/D Conversion Characteristics......................................................................................... 979 28.5 Flash Memory Characteristics ........................................................................................... 980 28.6 Usage Notes ....................................................................................................................... 981 Appendix A. B. C. D. .........................................................................................
Section 1 Overview Section 1 Overview 1.1 Features The core of each product in the H8S/2117R Group of CISC (complex instruction set computer) microcomputers is an H8S/2600 CPU, which has an internal 16-bit architecture. The H8S/2600 CPU provides upward-compatibility with the CPUs of other Renesas Technology-original microcomputers; H8/300, H8/300H, and H8S.
Section 1 Overview 1.1.2 Overview of Functions Table 1.1 lists the functions of this LSI in outline. Table 1.
Section 1 Overview Classification CPU Module/ Function Description MCU operating mode Mode 2: Single-chip mode (selected by driving the MD2 and MD0 pins low and MD1 pin high) Mode 4: Boot mode (selected by driving the MD2 high and MD1 and MD0 pins low) Mode 6: On-chip emulation mode (selected by driving the MD2 and MD1 pins high and the MD0 pin low) Note: MD0 is not available as a pin and is internally fixed to 0.
Section 1 Overview Classification Timer Module/ Function 8-bit PWM timer (PWMU) Description • • • • 14-bit PWM • timer • (PWMX) • 16-bit timer • pulse unit • (TPU) • • 8-bit timers A/B × six channels Selectable from four clock sources Cycle selectable for each channel Supports 8-bit single pulse mode, 16-bit single pulse mode, and 8-bit pulse division mode.
Section 1 Overview Classification Timer Module/ Function Description 8-bit timer (TMR) • • • Watchdog timer Watchdog timer (WDT) • Serial interface Serial communication interface with FIFO (SCIF) • • • • • Serial communication interface (SCI) • Smart card/ SIM 2 HighI C bus performance interface communication (IIC) • • • 8 bits × four channels (also works as 16 bits × two channels) Selectable from seven clocks: six internal clocks and one external clock Pulse output or PWM output with an ar
Section 1 Overview Classification Module/ Function FSI Highinterface performance communication (FSI) CIR interface (CIR) I/O ports Description • • • • • • • • • • • • • One channel Supports communications between this LCI and SPI flash memory Capable of operating as a master Supports LPC reset and LPC shut-down One channel Selectable from four sampling clocks: Three internal clocks and subclock 18-byte FIFO incorporated Input-only pins: 13 pins Input/output pins: 112 pins (TFP-144V and TLP-145V) 128 p
Section 1 Overview 1.2 List of Products Table 1.2 is the list of products, and figure 1.1 shows how to read the product name code. Table 1.2 List of Products Part No. ROM Capacity RAM Capacity Package R4F2117R 160 Kbytes 8 Kbytes PTQP0144LC-A Remarks Flash memory PLBG0176GA-A version PTLG0145JB-A Part no. R 4 F 2117R Indicates the product-specific number. H8S/2117R Indicates the type of ROM device.
Section 1 Overview SCI (2 channels) Smart Card I/F (2 channels) 8-bit PWM (12 channels) IIC (3 channels) 14-bit PWM (2 channels) 10-bit A/D converter (16 channels) LPC (4 channels) H-UDI 16-bit TPU (3 channels) Port 1 Port 2 P50/FTxD P51/FRxD P52/SCL0 P60/KIN0 P61/KIN1 P62/KIN2 P63/KIN3 P64/KIN4 P65/KIN5 P66/IRQ6/KIN6 P67/IRQ7/KIN7 P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 PD0/AN8 PD1/AN9 PD2AN10 PD3/AN11 PD4/AN12 PD5/AN13 PD6/AN14 PD7/AN15 Port 8 Figure 1.
Section 1 Overview Pin Assignments P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS PC0/TIOCA0/WUE8 PC1/TIOCB0/WUE9 PC2/TIOCC0/TCLKA/WUE10 PC3/TIOCD0/TCLKB/WUE11 PC4//TIOCA1/WUE12 PC5/TIOCB1/TCLKC/WUE13 PC6//TIOCA2/WUE14 PC7/TIOCB2/TCLKD/WUE15 VCC P67/IRQ7/KIN7 P66/IRQ6/KIN6 P65/KIN5 P64/KIN4 P63/KIN3 P62/KIN2 P61/KIN1 P60/KIN0 AVref AVCC P77/AN7 P76/AN6 P75/AN5 1.4.
Section 1 Overview 15 P12 P14 P17 P22 P25 PJ5 PC1 PC5 VCC PJ7 P62 AVref AVCC P77 P75 14 PJ4 P13 P15 P21 P24 P27 PC0 PC4 PJ6 P65 P61 AVref AVCC P74 P73 13 VSS VSS P11 P20 P26 VSS PC2 PC6 P67 P64 P60 NC P76 12 PB6 P10 PJ3 P16 P23 VSS PC3 PC7 P66 P63 NC NC P70 AVSS AVSS 11 PB3 PB4 PB5 PB7 PD0 PD3 PD1 PD2 10 PB1 PB0 PJ2 PB2 PD7 PD6 PD4 PD5 9 P32 P33 P31 P30 NC PG2 PG0 PG1 PG5 PI0 PG3 PG4 PF0 PI1 PG6 PG7 H8S/2117R Group PL
Section 1 Overview 13 P11 P13 P15 P20 P24 P26 PC1 PC3 PC7 P64 P60 12 P12 P10 P16 P22 P25 PC2 PC5 P67 P63 P61 P77 AVCC 11 PB7 VSS PB6 P14 P21 P23 PC0 PC6 P66 P62 AVref P71 P73 10 PB3 PB5 PB4 P17 P27 VSS PC4 VCC P65 PD2 P72 PD0 P70 9 P30 PB2 PB1 P31 AVSS PD4 PD1 8 P34 PB0 P32 P35 7 P80 P33 P82 6 P84 P81 5 P41 4 3 P75 P76 P74 * PD6 PG2 PD3 PG0 PD5 P36 PG3 PD7 PG6 PG1 P86 P37 PG4 PG7 PF2 PG5 P85 VSS P83 NC PF0 PF3
Section 1 Overview 1.4.2 Pin Assignment in Each Operating Mode Table 1.3 H8S/2117R Group Pin Assignment in Each Operating Mode Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No. Pin Name TFP144V BP176V TLP145V Single-Chip Mode ⎯ A3 ⎯ NC 141 D4 B3 PH4 142 B3 C4 PH5 143 A2 A3 XTAL 144 B2 A2 EXTAL Mode 2 (EXPE = 0) Notes: (N) in Pin No. indicates the pin is driven by NMOS push-pull/open drain and has 5 V input tolerance. (T) in Pin No. indicates the pin has 5 V input tolerance. * This pin is not supported by the system development tool (emulator). Rev. 2.00 Sep.
Section 1 Overview 1.4.3 Pin Functions Table 1.4 Pin Functions Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O Name and Function Power supply VCC 1, 36, 86 A1, J15, P1, P2 B1, M1, H10 Input Power supply pins. Connect all these pins to the system power supply. Connect the bypass capacitor between VCC and VSS (that is located near these pins). VCL 13 F1 E1 Input External capacitance pin for internal step-down power.
Section 1 Overview Pin No. Type Symbol Interrupts NMI H-UDI 8-bit timer (TMR_0, TMR_1, TMR_X, TMR_Y) TFP-144V BP-176V TLP-145V I/O Name and Function 11 F4 E3 Input Nonmaskable interrupt request input pin IRQ15 to 17, IRQ0 19 to 21, 47 to 50, 85, 84, 135 to 133, 24 to 22 G2, H2, J4, J3, N6, R6, P6, M7, J13, J12, B6, A6, C6, K4, J2, J1 F1, G4, H4, G1, L5, M6, N5, K5, H12, J11, C6, B5, A6, H2, G3, J4 Input These pins request a maskable interrupt.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No. Type 2 I C bus interface (IIC) I/O port Symbol TFP-144V BP-176V TLP-145V I/O Name and Function I C clock I/O pins. The output type is NMOS open-drain.
Section 1 Overview Pin No.
Section 1 Overview Pin No. Type Symbol I/O port PH5 to PH0 TFP-144V I/O C4, B3, A4, Input/ 142 to 140, B3, D4, 26, 12, 10 C4, K2, F3, J2, F2, E2 Output E1 PI7 to PI0 ⎯ PJ7 to PJ0 BP-176V TLP-145V ⎯ Name and Function 6-bit input/output pins G3, H4, ⎯ H3, K3, L5, M5, N7, N8 Input/ Output 8-bit input/output pins ⎯ Input/ Output 8-bit input/output pins K15, J14, F15, A14, C12, C10, B8, C5 (The output type of PI7 to PI0 is NMOS push-pull.) Notes: 1.
Section 1 Overview Rev. 2.00 Sep.
Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.
Section 2 CPU ⎯ 16 ÷ 8-bit register-register divide: 12 states ⎯ 16 × 16-bit register-register multiply: 3 states ⎯ 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode • Power-down state ⎯ Transition to power-down state by the SLEEP instruction ⎯ CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space ⎯ Normal mode supports the same 64-kbyte address space as the H8/300 CPU. ⎯ Advanced mode supports a maximum 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. • Address Space Linear access to a 64-kbyte maximum address space is provided.
Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Exception vector 1 Exception vector 2 Exception vector 3 Exception vector table Exception vector 4 Exception vector 5 Exception vector 6 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP (SP * 2 Reserved*1,*3 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3.
Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access to a 16-Mbyte maximum address space is provided. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used.
Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC).
Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Section 2 CPU Bit Bit Name Initial Value 1 V Undefined R/W R/W Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.
Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers.
Section 2 CPU Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 2.00 Sep.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
Section 2 CPU Symbol Description :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) 1 Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B BLD B BILD B C ⊕ [∼( of )] → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. (
Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc ⎯ Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA ⎯ Starts trap-instruction exception handling. RTE ⎯ Returns from an exception-handling routine. SLEEP ⎯ Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves general register or memory contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B ⎯ if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W ⎯ if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. Rev. 2.00 Sep.
Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats. • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand.
Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect.
Section 2 CPU 2.7.3 Register Indirect with Displacement⎯@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.
Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode* Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address H'000000 to H'FFFFFF 24 bits (@aa:24) Note: Normal mode is not available in this LSI. 2.7.
Section 2 CPU 2.7.8 Memory Indirect⎯@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long.
Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
Section 2 CPU 2.8 Processing States The H8S/2600 CPU has four main processing states: the reset state, exception handling state, program execution state and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
Section 2 CPU Program execution state SLEEP instruction with LSON = 0, PSS = 0, and SSBY = 1 SLEEP instruction with LSON = 0 and SSBY = 0 Request for exception handling End of exception handling Sleep mode Interrupt request Exception-handling state External interrupt request Software standby mode RES = high Power-down state*2 *1 Reset state Notes: 1. From any state, a transition to the reset state is made whenever the RES pin goes low.
Section 2 CPU 2.9 Usage Note 2.9.1 Notes on Using the Bit Operation Instruction Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte units after bit operation. Therefore, attention must be paid when these instructions are used for ports or registers including write-only bits. Instruction BCLR can be used to clear the flag in the internal I/O register to 0.
Section 2 CPU Rev. 2.00 Sep.
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports three operating modes (modes 2, 4, and 6). The operating mode is determined by the setting of the mode pins (MD2 and MD1). Table 3.1 shows the MCU operating mode selection. Table 3.
Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating modes. Table 3.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Data Bus Width Mode control register MDCR R/W ⎯ H'FFC5 8 System control register SYSCR R/W H'09 H'FFC4 8 Serial timer control register STCR R/W H'00 H'FFC3 8 System control register 3 SYSCR3 R/W H'60 H'FE7D 8 3.2.
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space. Bit Initial Bit Name Value R/W Description 7, 6 — R Reserved All 0 The initial value should not be changed.
Section 3 MCU Operating Modes Bit Initial Bit Name Value R/W Description 1 KINWUE R/W Keyboard Control Register Access Enable 0 When the RELOCATE bit is cleared to 0, this bit enables or disables CPU access for the keyboard matrix interrupt registers (KMIMRA and KMIMR), pullup MOS control register (KMPCR), and registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC, TCORA_X, TCORB_X, TCONRI, and TCONRS) of 8-bit timers (TMR_X and TMR_Y) 0: Enables CPU access for r
Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit Initial Bit Name Value R/W Description 7 IICX2 0 R/W I C Transfer Rate Select 2 to 0 6 IICX1 0 R/W 5 IICX0 0 R/W These bits control the IIC operation. These bits select the transfer rate in master mode together with bits 2 CKS2 to CKS0 in the I C bus mode register (ICMR).
Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Description 3 FLSHE 0 R/W Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, and FTDAR), power-down state control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and on-chip peripheral module control registers (PCSR). 0: When RELOCATE is 0, control registers of powerdown state and peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87.
Section 3 MCU Operating Modes 3.2.4 System Control Register 3 (SYSCR3) SYSCR3 selects the register map and interrupt vector. Bit Bit Name Initial Value R/W Description 7 — 0 R/W Reserved The initial value should not be changed. 6 EIVS* 1 R/W Extended interrupt Vector Select* Selects compatible mode or extended mode for the interrupt vector table. 0: H8S/2140B Group compatible vector mode 1: Extended vector mode For details, see section 5, Interrupt Controller.
Section 3 MCU Operating Modes 3.4 Address Map Figures 3.1 shows the address map in each operating mode. Mode 2 (EXPE = 0) Advanced mode Single-chip mode ROM: 160 Kbytes RAM: 8 Kbytes H'000000 On-chip ROM 160 Kbytes H'027FFF H'028000 Reserved area H'0FFFFF H'FF0000 Reserved area H'FFD07F H'FFD080 H'FFEFFF On-chip RAM 8064 bytes H'FFF800 Internal I/O registers 2 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 On-chip RAM 128 bytes Internal I/O registers 1 H'FFFFFF Figure 3.1 Address Map Rev. 2.00 Sep.
Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, illegal instruction, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.
Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to exception sources. Table 4.2 and table 4.3 list the exception sources and their vector addresses. The EIVS bit in the system control register 3 (SYSCR3) allows the selection of the H8S/2140B Group compatible vector mode or extended vector mode. Table 4.
Section 4 Exception Handling Vector Number Exception Source Vector Addresses Advanced Mode Internal interrupt* 24 ⎜ 29 H'000060 to H'000063 ⎜ H'000074 to H'000077 Reserved for system use 30 H'000078 to H'00007B Reserved for system use 31 H'00007C to H'00007F Reserved for system use 32 H'000080 to H'000083 External interrupt WUE15 to WUE8 33 H'000084 to H'000087 Internal interrupt* 34 ⎜ 55 H'000088 to H'00008B ⎜ H'0000DC to H'0000DF External interrupt IRQ8 56 H'0000E0 to H'0000E3 IRQ
Section 4 Exception Handling Table 4.
Section 4 Exception Handling Vector Number Exception Source Vector Addresses Normal Mode 34 ⎜ 55 H'000088 to H'00008B ⎜ H'0000DC to H'0000DF External interrupt IRQ8 56 H'0000E0 to H'0000E3 IRQ9 57 H'0000E4 to H'0000E7 IRQ10 58 H'0000E8 to H'0000EB IRQ11 59 H'0000EC to H'0000EF IRQ12 60 H'0000F0 to H'0000F3 IRQ13 61 H'0000F4 to H'0000F7 IRQ14 62 H'0000F8 to H'0000FB IRQ15 63 H'0000FC to H'0000FF 64 ⎜ 127 H'000100 to H'000103 ⎜ H'0001FC to H'0001FF Internal interrupt* Internal
Section 4 Exception Handling Figure 4.1 shows an example of the reset sequence.
Section 4 Exception Handling 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE8) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1.
Section 4 Exception Handling 4.6 Exception Handling by Illegal Instruction The exception handling by the illegal instruction starts when an undefined code is executed. The exception handling by the illegal instruction is always executable in the program execution state. The exception handling operates as follows: 1. The contents of the PC and CCR are saved in the stack. 2. The interrupt mask bit is updated. 3.
Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Advanced mode Normal mode SP CCR CCR* SP PC (16 bits) Notes: * CCR PC (24 bits) Ignored on return. Normal mode is not available in this LSI. Figure 4.2 Stack Status after Exception Handling Rev. 2.00 Sep.
Section 4 Exception Handling 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting in each module interrupt priority levels for all interrupt requests excluding NMI and address breaks.
Section 5 Interrupt Controller EIVS SYSCR3 CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input IRQ input IRQ input ISR ISCR IER Interrupt request Vector number Priority level determination KMIMR WUEMR KIN input WUE input I, UI KIN, WUE input CCR Internal interrupt sources WOVI0 to IBFI3 ICR Interrupt controller [Legend] Interrupt control register ICR: IRQ sense control register ISCR: IRQ enable register IER: IRQ status register ISR: KMIMR: Keyboard matrix interrupt mask register WUEMR: Wake-up eve
Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Pin Name I/O Function NMI Input Nonmaskable external interrupt pin Rising edge or falling edge can be selected IRQ15 to IRQ0, ExIRQ15 to ExIRQ6 Input Maskable external interrupt pins Rising-edge, falling-edge, or both-edge detection, or levelsensing, can be selected individually for each pin.
Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For details on system control register 3 (SYSCR3), see section 3.2.4, System Control Register 3 (SYSCR3). Table 5.
Section 5 Interrupt Controller Register Name Abbreviation R/W Initial Value Address Data Bus Width Wake-up sense control register WUESCR R/W H'00 H'FE84 8 Wake-up input interrupt status register WUESR R/W H'00 H'FE85 8 Wake-up enable register WER R/W H'00 H'FE86 8 Note: 5.3.1 1. Address in the upper cell: when RELOCATE = 0, address in the lower cell: when RELOCATE = 1 2.
Section 5 Interrupt Controller Table 5.
Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE bit are set to 1, an address break is requested. Bit Bit Name Initial Value R/W Description 7 CMF Undefined R Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Clearing condition] When an exception handling is executed for an address break interrupt.
Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. • BARA Bit Bit Name Initial Value R/W Description 7 to 0 A23 to A16 All 0 Addresses 23 to 16 R/W The A23 to A16 bits are compared with A23 to A16 in the internal address bus.
Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ6.
Section 5 Interrupt Controller • ISCR16L Bit Bit Name Initial Value R/W Description 7 IRQ11SCB 0 R/W IRQn Sense Control B 6 IRQ11SCA 0 R/W IRQn Sense Control A 5 IRQ10SCB 0 R/W BA 4 IRQ10SCA 0 R/W 3 IRQ9SCB 0 R/W 00: Interrupt request generated at low level of IRQn or ExIRQn input 2 IRQ9SCA 0 R/W 1 IRQ8SCB 0 R/W 0 IRQ8SCA 0 R/W 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn inp
Section 5 Interrupt Controller • ISCRL Bit Bit Name Initial Value R/W Description 7 IRQ3SCB 0 R/W IRQn Sense Control B 6 IRQ3SCA 0 R/W IRQn Sense Control A 5 IRQ2SCB 0 R/W BA 4 IRQ2SCA 0 R/W 3 IRQ1SCB 0 R/W 00: Interrupt request generated at low level of IRQn input 2 IRQ1SCA 0 R/W 1 IRQ0SCB 0 R/W 0 IRQ0SCA 0 R/W 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated a
Section 5 Interrupt Controller 5.3.5 IRQ Enable Registers (IER16, IER) The IER registers enable and disable interrupt requests IRQ15 to IRQ0. • IER16 Bit Bit Name Initial Value R/W Description 7 IRQ15E 0 R/W IRQn Enable 6 IRQ14E 0 R/W 5 IRQ13E 0 R/W The IRQn interrupt request is enabled when this bit is 1.
Section 5 Interrupt Controller 5.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests.
Section 5 Interrupt Controller • ISR Bit Bit Name Initial Value R/W Description 7 IRQ7F 0 R/(W)* [Setting condition] 6 IRQ6F 0 5 IRQ5F 0 R/(W)* When the interrupt source selected by the ISCR R/(W)* registers occurs 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F 0 R/(W)* [Clearing conditions] R/(W)* • When writing 0 to IRQnF flag after reading IRQnF = 1 R/(W)* • When interrupt exception handling is executed R/(W)* when low-level detection is set and IRQn or R/(W)* ExIRQn inpu
Section 5 Interrupt Controller 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR) The KMIMR and WUEMR registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0) and wake-up event interrupt inputs (WUE15 to WUE8).
Section 5 Interrupt Controller • WUEMR Bit Bit Name Initial Value R/W Description 7 WUEMR15 1 R/W Wake-Up Event Interrupt Mask 6 WUEMR14 1 R/W 5 WUEMR13 1 R/W These bits enable or disable a wake-up event input interrupt request (WUE15 to WUE8). 4 WUEMR12 1 R/W 0: Enables a wake-up event input interrupt request 3 WUEMR11 1 R/W 1: Disables a wake-up event input interrupt request 2 WUEMR10 1 R/W 1 WUEMR9 1 R/W 0 WUEMR8 1 R/W Rev. 2.00 Sep.
Section 5 Interrupt Controller Figure 5.2 shows the relation between the IRQ7 and IRQ6 interrupts, KMIMR, and KMIMRA in H8S/2140B Group compatible vector mode. The relation in extended vector mode is shown in figure 5.3.
Section 5 Interrupt Controller In H8S/2140B Group compatible vector mode, interrupt input from the IRQ7 pin is ignored when even one of the KMIMR15 to KMIMR8 bits is cleared to 0. If the KIN7 to KIN0 pins or KIN15 to KIN8 pins are specified to be used as key-sensing interrupt input pins and wake-up event interrupt input pins, the interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7) must be set to low-level sensing or falling-edge sensing.
Section 5 Interrupt Controller 5.3.8 IRQ Sense Port Select Register 16 (ISSR16) IRQ Sense Port Select Register (ISSR) ISSR16 and ISSR select the IRQ15 to IRQ0 interrupt external input from the IRQ15 to IRQ7 pins and ExIRQ15 to ExIRQ7 pins.
Section 5 Interrupt Controller 5.3.9 Wake-Up Sense Control Register (WUESCR) Wake-Up Input Interrupt Status Register (WUESR) Wake-Up Enable Register (WER) WUESCR selects the interrupt source of the wake-up event interrupt inputs (WUE15 to WUE8). WUESR is an interrupt request flag register. WER enables/disables interrupts.
Section 5 Interrupt Controller • WER Bit Bit Name Initial Value R/W Description 7 WUEE 0 R/W WUE Enable The WUE interrupt request is enabled when this bit| is 1. 0: Wake-up input interrupt request is disabled 1: Wake-up input interrupt request is enabled 6 to 0 ⎯ All 0 R/W Reserved The initial values should not be changed. 5.4 Interrupt Sources 5.4.1 External Interrupt Sources The interrupt sources of external interrupts are NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to WUE8.
Section 5 Interrupt Controller When the interrupts are requested while IRQ15 to IRQ0 interrupt requests are generated at low level of IRQn input, hold the corresponding IRQ input at low level until the interrupt handling starts. Then put the relevant IRQ input back to high level within the interrupt handling routine and clear the IRQnF bit (n = 15 to 0) in ISR to 0. If the relevant IRQ input is put back to high level before the interrupt handling starts, the relevant interrupt may not be executed.
Section 5 Interrupt Controller ⎯ When using the IRQ6 pin as the IRQ6 interrupt input pin, the KMIMR6 bit must be cleared to 0. When using the IRQ7 pin as the IRQ7 interrupt input pin, the KMIMR15 to KMIMR8 bits must all be set to 1. If even one of these bits is cleared to 0, the IRQ7 interrupt input from the IRQ7 pin is ignored. • Extended vector mode (EIVS = 1 in SYSCR3) ⎯ Interrupts KIN15 to KIN8 and KIN7 to KIN0, each form a group.
Section 5 Interrupt Controller 5.4.2 Internal Interrupt Sources Internal interrupts issued from the on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller.
Section 5 Interrupt Controller Origin of Interrupt Source Vector Address Name Vector Number Advanced Mode ICR Priority High — Reserved for system use 24 H'000060 — WDT_0 WOVI0 (Interval timer) 25 H'000064 ICRA1 WDT_1 WOVI1 (Interval timer) 26 H'000068 ICRA0 — Address break 27 H'00006C — A/D converter ADI (A/D conversion end) 28 H'000070 ICRB7 — 29 H'000074 — ⏐ 32 ⏐ H'000080 Reserved for system use External pin WUE15 to WUE8 33 H'000084 ICRD4 TPU_0 TGI0A (TGR0A inpu
Section 5 Interrupt Controller Origin of Interrupt Source Vector Address Name Vector Number Advanced Mode ICR Priority TCM_2 TICI2 (Input capture) TCMI2 (Compare match) TOVMI2 (Cycle overflow) TUDI2 (Cycle underflow) TOVI2 (Overflow) 50 H'0000C8 ICRB6 High TCM_3 TICI3 (Input capture) TCMI3 (Compare match) TOVMI3 (Cycle overflow) TUDI3 (Cycle underflow) TOVI3 (Overflow) 51 H'0000CC TDP_0 TICI0 (Input capture) TCMI0 (Compare match) TPDMXI0 (Cycle overflow) TPDMNI0 (Cycle underflow) TWDMNI0 (P
Section 5 Interrupt Controller Origin of Interrupt Source Vector Address Name Vector Number TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) 64 65 66 — Reserved for system use 67 H'00010C — TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) 68 69 70 H'000110 H'000114 H'000118 ICRB2 — Reserved for system use 71 H'00011C — TMR_X TMR_Y CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture) CMIAX (Compare match A) CMIBX
Section 5 Interrupt Controller Origin of Interrupt Source Vector Address Vector Number Advanced Mode ICR Priority KBIA (Reception completion A) KBIB (Reception completion B) KBIC (Reception completion C) KBTIA (Transmission completion A)/ KBCA (1st KCLKA) KBTIB (Transmission completion B)/ KBCB (1st KCLKB) KBTIC (Transmission completion C)/ KBCC (1st KCLKC) KBID (Reception completion D) KBTID (Transmission completion D)/KBCD (1st KCLKD) 96 97 98 99 H'000180 H'000184 H'000188 H'00018C ICRB0 High 10
Section 5 Interrupt Controller Table 5.
Section 5 Interrupt Controller Origin of Interrupt Source Vector Address Vector Number Advanced Mode ICR Priority TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TGI2V (Overflow 1) TGI2U (Underflow 2) 43 H'0000AC ICRD1 High 44 H'0000B0 45 46 H'0000B4 H'0000B8 — Reserved for system use 47 H'0000BC — TCM_0 TICI0 (Input capture) TCMI0 (Compare match) TOVMI0 (Cycle overflow) TUDI0 (Cycle underflow) TOVI0 (Overflow) 48 H'0000C0 ICRB6 TCM_1 TICI1 (Input
Section 5 Interrupt Controller Origin of Interrupt Source Name Vector Number Vector Address Advanced Mode ICR TDP_2 TICI2 (Input capture) TCMI2 (Compare match) TPDMXI2 (Cycle overflow) TPDMNI2 (Cycle underflow) TWDMNI2 (Pulse width lower limit underflow) TWDMXI2 (Pulse width upper limit overflow) TOVI2 (Overflow) 54 H'0000D8 ICRB5 High — Reserved for system use 55 H'0000DC — External pin IRQ8 IRQ9 IRQ10 IRQ11 56 57 58 59 H'0000E0 H'0000E4 H'0000E8 H'0000EC ICRD7 IRQ12 IRQ13 IRQ14 IRQ15 6
Section 5 Interrupt Controller Origin of Interrupt Source Name Vector Address Vector Number Advanced Mode ICR SCI_2 ERI2 (Reception error) RXI2 (Reception completion) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) 88 89 90 91 H'000160 H'000164 H'000168 H'00016C ICRC5 High IIC_0 IICI0 (1-byte transmission/reception completion) 92 H'000170 ICRC4 CIR RENDI (Reception end) OVEI (Overrun error) REPI (Repeat detection) FREI (Framing error) ABI (Abort) HEADFI (Header detection) 93 H'00
Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI and address break interrupts are always accepted except for in the reset state. The interrupt control mode is selected by SYSCR. Table 5.7 shows the interrupt control modes. Table 5.
Section 5 Interrupt Controller (1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.8 shows the interrupts selected in each interrupt control mode. Table 5.
Section 5 Interrupt Controller Table 5.9 shows operations and control signal functions in each interrupt control mode. Table 5.9 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Control Mode INTM1 0 1 0 Interrupt Acceptance Control 3-Level Control Setting INTM0 I UI ICR Default Priority Determination 0 Ο IM — PR Ο 1 Ο IM IM PR Ο [Legend] Ο: Interrupt operation control is performed IM: Used as an interrupt mask bit PR: Priority is set —: Not used 5.6.
Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ICR setting. • An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending.
Section 5 Interrupt Controller Figure 5.9 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI No No An interrupt with interrupt control level 1? Hold pending Yes IRQ0 Yes No No IRQ0 No Yes IRQ1 No IRQ1 Yes Yes IBFI3 IBFI3 Yes Yes I=0 No I=0 Yes No UI = 0 No Yes Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 2.00 Sep.
Rev. 2.00 Sep. 28, 2009 Page 124 of 994 REJ09B0452-0200 (1) (2) (4) (3) Instruction prefetch address (Not executed. Address is saved as PC contents, becoming return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.10 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 5.10 Interrupt Response Times No.
Section 5 Interrupt Controller 5.7 Address Breaks 5.7.1 Features With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed. This function can be used to detect the beginning of execution of a bug location in the program, and branch to a correction routine. 5.7.2 Block Diagram Figure 5.
Section 5 Interrupt Controller 5.7.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority. When the interrupt is accepted, interrupt exception handling is started on completion of the currently executing instruction.
Section 5 Interrupt Controller • Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Vector fetch Stack save Internal Instruction operation fetch φ Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 Interrupt exeption handling NOP NOP NOP execution execution execution Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Bre
Section 5 Interrupt Controller 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction.
Section 5 Interrupt Controller 5.8.2 Instructions for Disabling Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.
Section 5 Interrupt Controller 5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode • When the pins (IRQ15 to IRQ0, ExIRQ15 to ExIRQ6, KIN15 to KIN0, and WUE15 to WUE8) are used as external input pins in software standby mode or watch mode, the pins should not be left floating. • When the external interrupt pins (IRQ7, IRQ6, ExIRQ15 to ExIRQ8, KIN7 to KIN0, and WUE15 to WUE8) are used in software standby and watch modes, the noise canceller should be disabled. 5.8.
Section 5 Interrupt Controller Rev. 2.00 Sep.
Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to the control registers for the bus controller. 6.1 Register Descriptions The bus controller has the following registers. Table 6.
Section 6 Bus Controller (BSC) 6.1.2 Wait State Control Register (WSCR) Bit Initial Bit Name Value R/W Description 7, 6 — All 1 R/W Reserved 5 ABW 1 R/W The initial value should not be changed. Bus Width Control The initial value should not be changed. 4 AST 1 R/W Access State Control The initial value should not be changed. 3 WMS1 0 R/W Wait Mode Select 1 and 0 2 WMS0 0 R/W The initial value should not be changed.
Section 7 I/O Ports Section 7 I/O Ports Table 7.1 lists the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port input data register (PIN) used to read the pin states. Port E does not have a DR or a DDR register.
Section 7 I/O Ports Table 7.
Section 7 I/O Ports Function LED Drive Input Pull- Capability Port Port 4 (5 mA Sink Noise Function Current) Canceler ⎯ ⎯ ⎯ ⎯ ⎯ O ⎯ O Description Bit I/O Input Output General I/O 7 TCMCKI3/ PWX1/PWMU5B ⎯ P47 port also functioning as On-Chip up MOS TCMMCI3 6 P46 TCMCYI3 PWX0/PWMU4B 5 P45 TCMCKI2/ PWMU3B PWMX and PWMU_B TCMMCI2 outputs, TCM input, and 4 P44 TCMCYI2 TMO1/PWMU2B 3 P43/SCK2 TMI1/TCMCKI1/ ⎯ TMR_0, TMR_1, TCMMCI1 IIC_1, and SCI_2 inputs/outputs 2
Section 7 I/O Ports Function LED Drive Input Pull- Capability Output Function Current) Canceler ⎯ P77/AN7 ⎯ ⎯ ⎯ ⎯ ⎯ P76/AN6 ⎯ A/D converter 5 ⎯ P75/AN5 ⎯ analog input 4 ⎯ P74/AN4 ⎯ 3 ⎯ P73/AN3 ⎯ 2 ⎯ P72/AN2 ⎯ 1 ⎯ P71/AN1 ⎯ 0 ⎯ P70/AN0 ⎯ P86/SCK1/ IRQ5 ⎯ ⎯ ⎯ ⎯ O ⎯ ⎯ Description Port 7 General input 7 port also 6 functioning as General I/O Bit I/O 6 port also functioning as SCL1 5 P85 RxD1/IRQ4 ⎯ input, IIC_1, 4 P84 IRQ3 TxD1 SCI_1, and 3 P8
Section 7 I/O Ports Function LED Drive Input Pull- Capability Port Port A Bit I/O Input Output Function Current) Canceler General I/O 7 PA7/PS2CD KIN15 ⎯ ⎯ ⎯ ⎯ 6 PA6/PS2CC KIN14 ⎯ 5 PA5/PS2BD KIN13 ⎯ 4 PA4/PS2BC KIN12 ⎯ 3 PA3/PS2AD KIN11 ⎯ 2 PA2/PS2AC KIN10 ⎯ 1 PA1/PS2DD KIN9 ⎯ 0 PA0/PS2DC KIN8 ⎯ 7 PB7 ⎯ RTS/FSISS O ⎯ ⎯ 6 PB6 CTS FSICK 5 PB5 FSIDI DTR 4 PB4 DSR FSIDO 3 PB3 DCD PWMU1B 2 PB2 RI PWMU0B 1 PB1/LSCI ⎯ ⎯ 0 PB0/LSMI ⎯ ⎯
Section 7 I/O Ports Function LED Drive Input Pull- Capability Port Port D Bit I/O Input Output Function Current) Canceler General I/O 7 PD7 AN15 ⎯ O O ⎯ 6 PD6 AN14 ⎯ A/D converter 5 PD5 AN13 ⎯ 4 PD4 AN12 ⎯ 3 PD3 AN11 ⎯ 2 PD2 AN10 ⎯ 1 PD1 AN9 ⎯ 0 PD0 AN8 ⎯ ⎯ PE4* /ETMS ⎯ ⎯ ⎯ O ⎯ ⎯ functioning as analog input General input 4 port also 1 ⎯ 1 ETDO 1 3 ⎯ 2 ⎯ PE2* /ETDI ⎯ 1 ⎯ 1 PE1* /ETCK ⎯ input/output 0 ⎯ PE0/ExEXCL ⎯ General I/O 7 P
Section 7 I/O Ports Function LED Drive Input Pull- Capability Port Description Port G General I/O port also functioning as interrupt and TDP inputs, TMR_X and TMR_Y inputs, and IIC0 to IIC2 Bit I/O Input (5 mA Sink Noise Output Function Current) Canceler ⎯ ⎯ O O ⎯ ⎯ ⎯ ⎯ ⎯ 7 PG7/ExSCLB ExIRQ15 ⎯ 6 PG6/ExSDAB ExIRQ14 ⎯ 5 PG5/ExSCLA ExIRQ13 ⎯ 4 PG4/ExSDAA ExIRQ12 ⎯ 3 PG3/SCL2 ExIRQ11 ⎯ 2 PG2/SDA2 ExIRQ10 ⎯ PG1 TMIY1/ ⎯ inputs/outputs 1 On-Chip up MOS TDPCKI1/TDPM
Section 7 I/O Ports Function LED Drive Input Pull- Capability Port Port J Description General I/O port (5 mA Sink Noise Input Output Function Current) Canceler 2 ⎯ ⎯ O ⎯ ⎯ 2 ⎯ ⎯ 2 ⎯ ⎯ 2 ⎯ ⎯ 2 ⎯ ⎯ 2 ⎯ ⎯ 1 2 PJ1* ⎯ ⎯ 0 PJ0*2 ⎯ ⎯ Bit I/O 7 6 5 4 3 2 PJ7* PJ6* PJ5* PJ4* PJ3* PJ2* Notes: 1. Not supported by the system development tool (emulator). 2. Not supported by TFP-144V and TLP-145V. Rev. 2.00 Sep.
Section 7 I/O Ports 7.1 Register Descriptions Table 7.2 lists each port registers. Table 7.
Section 7 I/O Ports 7.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to J) DDR specifies the port input or output for each bit. The upper five bits in P5DDR, the upper one bit in P8DDR, and the upper two bits in PHDDR are reserved. (1) PORTS = 0 Bit Bit Name Initial Value R/W Description 7 Pn7DDR 0 W 6 Pn6DDR 0 W The corresponding pins act as output ports when these bits are set to 1 and act as input ports when cleared to 0.
Section 7 I/O Ports 7.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9) DR is a register that stores output data of the pins to be used as the general output port. Since the P96DR bit is determined by the state of the P96 pin, the initial value is undefined. The upper five bits in P5DR and the upper one bit in P8DR are reserved. Bit Bit Name Initial Value R/W Description 7 Pn7DR 0 R/W 6 Pn6DR 0 R/W PnDR stores output data for the pins that are used as the general output port.
Section 7 I/O Ports 7.1.4 Pull-Up MOS Control Register (PnPCR) (n = 1 to 3, 9, B to D, F, H, and J) Pull-Up MOS Control Register (KMPCR) (Port 6) PCR is a register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in the input state, the input pull-up MOS corresponding to the bit in PCR is turned on. Table 7.3 shows the input pull-up MOS state. The upper two bits in P9PCR and the upper two bits in PHPCR are reserved.
Section 7 I/O Ports Table 7.3 Input Pull-Up MOS State (1) • Port 1 to 3, 6, 9, and J Port Pin State Port 1 Port output Port input Port 2 Off Off Port 6 Port output (KMPCR) Port input Port 9 Port output Port input Off On/Off Off Off On/Off Off Off On/Off Off Off Port output Port input On/Off Off Port output Port input Port J Software Standby Mode Other Operation Port output Port input Port 3 Reset On/Off Off Off On/Off [Legend] Off: The input pull-up MOS is always off.
Section 7 I/O Ports Table 7.3 Input Pull-Up MOS State (2) • Port B to D, F, and H Port Pin State Port B Port output Reset Port input Port C Off On/Off Off Off On/Off Off Off Port output Port input On/Off Off Port output Port input Port H Off Port output Port input Port F Off Port output Port input Port D Software Standby Mode Other Operation On/Off Off Off On/Off [Legend] Off: The input pull-up MOS is always off.
Section 7 I/O Ports 7.1.5 Output Data Register (PnODR) (n = A to D and F to J) ODR is a register that stores output data for ports. The upper two bits in PHODR are reserved. Bit Bit Name Initial Value R/W Description 7 Pn7ODR 0 R/W 6 Pn6ODR 0 R/W ODR stores the output data for the pins that are used as the general output port. 5 Pn5ODR 0 R/W 4 Pn4ODR 0 R/W 3 Pn3ODR 0 R/W 2 Pn2ODR 0 R/W 1 Pn1ODR 0 R/W 0 Pn0ODR 0 R/W 7.1.
Section 7 I/O Ports Noise Canceler Decision Control Register (PnNCMC) (n = 6, C, and G) 7.1.7 NCMC controls whether 1 or 0 is expected for the input signal to port n pins in bit units. Bit Bit Name Initial Value R/W Description 7 Pn7NCMC 0 R/W 6 Pn6NCMC 0 R/W 1 expected: 1 is stored in the port data register when 1 is input stably.
Section 7 I/O Ports φ/2, φ/32, φ/8192, φ/16384, φ/32768, φ/65536, φ/131072, φ/262144 Sampling clock selection Pin input Latch Latch Latch Matching detection circuit t Latch Port data register Interrupt input Keyboard input t Sampling clock Figure 7.1 Noise Cancel Circuit P6n input PCn input PGn input 1 expected P6n input PCn input PGn input 0 expected P6n input PCn input PGn input (n = 7 to 0) Figure 7.2 Schematic View of Noise Cancel Operation Rev. 2.00 Sep.
Section 7 I/O Ports 7.1.9 Port Nch-OD Control Register (PnNOCR) (n = C, D, and F to J) The individual bits of NOCR specify output driver type for the pins of port n that is specified as output. The upper two bits in PHNOCR are reserved. Bit Bit Name Initial Value R/W Description 7 Pn7NOCR 0 R/W 6 Pn6NOCR 0 R/W 0: CMOS (Ports G and I are NMOS push-pull output) 5 Pn5NOCR 0 R/W 4 Pn4NOCR 0 R/W 3 Pn3NOCR 0 R/W 2 Pn2NOCR 0 R/W 1 Pn1NOCR 0 R/W 0 Pn0NOCR 0 R/W Rev. 2.
Section 7 I/O Ports 7.1.10 Pin Functions The pin function is switched according to the setting of the PORTS bit in PTCNT2. (Ports B to D, F, and H) (1) PORTS = 0 DDR 0 NOCR ⎯ ODR 0 1 0 1 1 0 1 0 On N-ch. driver Off On Off P-ch. driver Off Off On Input pull-up MOS Off Pin function (2) On 1 Off Off Off Input pin Output pin PORTS = 1 DDR 0 NOCR ⎯ ODR ⎯ PCR 0 1 0 0 1 1 Off On Off P-ch. Driver Off Off On Pin Function Off On Input pin 1 On Off ⎯ 1 N-ch.
Section 7 I/O Ports 7.2 Output Buffer Control This section describes the output priority of each pin. The name of each peripheral module pin is followed by “_OE”. This (for example: TIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). Table 7.4 lists each port output signal's valid setting. For details on the corresponding output signals, see the register description of each peripheral module. 7.2.
Section 7 I/O Ports 7.2.3 (1) Port 3 P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The pin function is switched as shown below according to the combination of the FSILIE bit in SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 and LPC3E to LPC1E bits in HICR0 of the LPC, and the P3nDDR bit. LPCENABLE in the following table is expressed by the following logical expression.
Section 7 I/O Ports (2) P46/PWX0/PWMU4B/TCMCYI3 The pin function is switched as shown below according to the combination of the PWMX and PWMU and the P46DDR bit.
Section 7 I/O Ports (4) P44/TMO1/PWMU2B/TCMCYI2 The pin function is switched as shown below according to the combination of the TMR and PWMU and the P44DDR bit.
Section 7 I/O Ports (6) P42/SDA1/TCMCYI1 The pin function is switched as shown below according to the combination of the IIC1AS and IIC1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, and the P42DDR bit. When the TCMIPE bit in TCMIER_1 of TCM_1 is set to 1, TCMCYI1 functions as an input pin.
Section 7 I/O Ports (8) P40/TMI0/TxD2/TCMCYI0 The pin function is switched as shown below according to the combination of the TMR and the SCI and the P40DDR bit. Setting SCI I/O Port Pin Function TxD2_OE P40DDR SCI TxD2 output 1 ⎯ I/O port P40 output 0 1 P40 input (initial setting) 0 0 Module Name 7.2.5 (1) Port 5 P52/SCL0 The pin function is switched as shown below according to the combination of the IIC0AS and IIC0BS bits in PTCNT1, ICE bit in ICCR of IIC_0, and the P52DDR bit.
Section 7 I/O Ports (2) P51/FRxD The pin function is switched as shown below according to the SCIFOE1 bit in SCIFCR of the SCIF and the SCIFE bit in HICR5 of the SCIF, and the P51DDR bit.
Section 7 I/O Ports 7.2.6 (1) Port 6 P67/KIN7/IRQ7 When the KMIM7 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN7 input pin. When the ISS7 bit in ISSR is cleared to 0 and the IRQ7E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ7 input pin. The pin function is switched as shown below according to the state of the P67DDR bit.
Section 7 I/O Ports (3) P65/KIN5, P64/KIN4, P63/KIN3, P62/KIN2, P61/KIN1, P60/KIN0 When the KMIMn bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KINn input pin. The pin function is switched as shown below according to the state of the P6nDDR bit. Setting I/O Port Module Name Pin Function P6nDDR I/O port P6n output 1 P6n input (initial setting) 0 (n = 5 to 0) 7.2.
Section 7 I/O Ports 7.2.8 (1) Port 8 P86/IRQ5/SCK1/SCL1 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, CKE0 and CKE1 bits in SCR, IIC1AS and IIC1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, and the P86DDR bit. When the ISS5 bit in ISSR is cleared to 0 and the IRQ5E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ5 input pin.
Section 7 I/O Ports (3) P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the register setting of the SCI and the P84DDR bit.
Section 7 I/O Ports (5) P82/CLKRUN The pin function is switched as shown below according to the combination of the FSILIE bit in SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 of the LPC, LPC3E to LPC1E bits in HICR0, and the P82DDR bit. LPCENABLE in the following table is expressed by the following logical expression.
Section 7 I/O Ports (7) P80/PME The pin function is switched as shown below according to the combination of the register setting of the LPC and the P80DDR bit. Setting LPC I/O Port Pin Function PME_OE P80DDR LPC PME output 1 ⎯ I/O port P80 output 0 1 P80 input (initial setting) 0 0 Module Name 7.2.9 (1) Port 9 P97/IRQ15/SDA0 The pin function is switched as shown below according to the combination of the IIC0AS and IIC0BS bits in PTCNT1, ICE bit in ICCR of IIC_0, and the P97DDR bit.
Section 7 I/O Ports (2) P96/φ/EXCL The pin function is switched as shown below according to the combination of the register settings of the EXCLS bit in PTCNT0, EXCLE bit in LPWRCR, and the P96DDR bit. Setting I/O Port Module Name Pin Function P96DDR Clock φ output 1 I/O port P96 input (initial setting) 0 (3) P95/IRQ14, P94/IRQ13, P93/IRQ12, P92/IRQ0, P91/IRQ1, P90/IRQ2 The pin function is switched as shown below according to the state of the P9nDDR bit.
Section 7 I/O Ports 7.2.10 (1) Port A PA7/KIN15/PS2CD, PA6/KIN14/PS2CC, PA5/KIN13/PS2BD, PA4/KIN12/PS2BC, PA3/KIN11/PS2AD, PA2/KIN10/PS2AC, PA1/KIN9/PS2DD, PA0/KIN8/PS2DC The pin function is switched according to the combination of the register setting of PS2 and the PAnDDR bit. When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KINm input pin.
Section 7 I/O Ports 7.2.11 (1) Port B PB7/RTS/FSISS The pin function is switched as shown below according to the combination of the SCIFE bit in HICR5 of LPC, the FSIE bit in FSICR1 of FSI and the PB7DDR bit.
Section 7 I/O Ports (3) PB5/DTR/FSIDI The pin function is switched as shown below according to the combination of the SCIFE bit in HICR5 of LPC, the FSIE bit in FSICR1of FSI and the PB5DDR bit.
Section 7 I/O Ports (5) PB3/DCD/PWMU1B The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PB3DDR bit. Setting PWMU I/O Port Pin Function PWMU1B_OE PB3DDR PWMU PWMU1B output 1 1 I/O port PB3 output 0 1 PB3 input (initial setting) ⎯ 0 Module Name (6) PB2/RI/PWMU0B The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PB2DDR bit.
Section 7 I/O Ports (7) PB1/LSCI The pin function is switched as shown below according to the combination of the register setting of the LPC and the PB1DDR bit. Setting LPC I/O Port Pin Function LSCI_OE PB1DDR LPC LSCI output 1 ⎯ I/O port PB1 output 0 1 PB1 input (initial setting) 0 0 Module Name (8) PB0/LSMI The pin function is switched as shown below according to the combination of the register setting of the LPC and the PB0DDR bit.
Section 7 I/O Ports 7.2.12 (1) Port C PC7/WUE15/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC7DDR bit. When the WUEMR15 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE15 input pin. This pin functions as the TCLKD input when TPSC2 to TPSC0 in TCR_0 is B'111. Also, when channel 2 is set to phase counting mode, this pin functions as the TCLKD input.
Section 7 I/O Ports (3) PC5/WUE13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC5DDR bit. When the WUEMR13 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE13 input pin. This pin functions as TCLKC input when TPSC2 to TPSC0 in TCR_0 or TCR_2 is set to B'110 or when channel 2 is set to phase counting mode.
Section 7 I/O Ports (5) PC3/WUE11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC3DDR bit. When the WUEMR11 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE11 input pin. This pin functions as TCLKB input when TPSC2 to TPSC0 in any of TCR_0 to TCR_2 are set to B'101 or when channel 1 is set to phase counting mode.
Section 7 I/O Ports (7) PC1/WUE9/TIOCB0 The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC1DDR bit. When the WUEMR9 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE9 input pin. This pin functions as TIOCB0 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOB3 to IOB0 in TIORH_0 are set to B'10xx. (x: Don’t care.
Section 7 I/O Ports 7.2.13 (1) Port D PD7/AN15, PD6/AN14, PD5/AN13, PD4/AN12, PD3/AN11, PD2/AN10, PD1/AN9, PD0/AN8 The pin function is switched as shown below according to the state of the PDnDDR bit. When this pin is used as an analog input pin, do not set the pin as output. Setting I/O Port Module Name Pin Function PDnDDR I/O port PDn output 1 PDn input (initial setting) 0 (n = 7 to 0) 7.2.
Section 7 I/O Ports (2) PE0/ExEXCL The pin function is switched as shown below according to the combination of the EXCLS bit in PTCNT0 and EXCLE bit in LPWRCR. When the EXCLS bit in PTCNT0 and EXCLE bit in LPWRCR are set to 1, this pin can be used as the ExEXCL input pin. Setting Module Name I/O port 7.2.
Section 7 I/O Ports (2) PF3/TMOX/IRQ11/TDPCKI0/TDPMCI0 The pin function is switched as shown below according to the combination of the register setting of the TMR and the PF3DDR bit. When the PMMS bit in TDPCR2_0 of TDP0 is set to 1, this pin can be used as the TDPMCI0 input pin. When the external clock is selected by the CKS3 to CKS0 bits in TDPCR1_0 of TDP0, this pin is used as the TDPCKI0 input pin. Do not set input of TDPCKI0 and TDPMCI0 at the same time.
Section 7 I/O Ports (4) PF1/IRQ9/PWMU1A The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PF1DDR bit. When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ9 input pin.
Section 7 I/O Ports 7.2.16 (1) Port G PG7/ExSCLB/ExIRQ15 The pin function is switched as shown below according to the combination of the register setting of PTCNT1 and the PG7DDR bit. When the ISS15 bit in ISSR16 is set to 1 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ15 input pin.
Section 7 I/O Ports (3) PG5/ExSCLA/ExIRQ13 The pin function is switched as shown below according to the combination of the register setting of PTCNT1 and the PG5DDR bit. When the ISS13 bit in ISSR16 is set to 1 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ13 input pin.
Section 7 I/O Ports (5) PG3/SCL2/ExIRQ11 The pin function is switched as shown below according to the combination of the register setting of the IIC and the PG3DDR bit. When the ISS11 bit in ISSR16 is set to 1 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ11 input pin.
Section 7 I/O Ports (7) PG1/ExIRQ9/TMIY/TDPCKI1/TDPMCI1 The pin function is switched as shown below according to the state of the PG1DDR bit. When the PMMS bit in TDPCR2_1 of the TDP is set to 1, this pin is used as the TDPMCI1 input pin. When the external clock is selected by the CKS2 to CKS0 bits in TDPCR1_1 of the TDP, this pin is used as the TDPCKI1 input pin. Do not set input of TDPCKI1 and TDPMCI1 at the same time.
Section 7 I/O Ports 7.2.17 (1) Port H PH5, PH4, PH3 The pin function is switched as shown below according to the state of the PHnDDR bit. Setting Module Name I/O port I/O Port Pin Function PHnDDR PHn output 1 PHn input (initial setting) 0 (n = 5 to 3) (2) PH2/CIRI The pin function is switched as shown below according to the combination of the register setting of CIR and the PH2DDR bit.
Section 7 I/O Ports (3) PH1/ExIRQ7/TDPCKI2/TDPMCI2 The pin function is switched as shown below according to the state of the PH1DDR bit. When the PMMS bit in TDPCR2_2 of the TDP is set to 1, this pin is used as the TDPMCI2 input pin. When the external clock is selected by the CKS2 to CKS0 bits in TDPCR1_2 of the TDP, this pin is used as the TDPCKI2 input pin. Do not set input of TDPCKI2 and TDPMCI2 at the same time.
Section 7 I/O Ports 7.2.18 (1) Port I PI7, PI6, PI5, PI4, PI3, PI2, PI1, PI0 The pin function is switched as shown below according to the state of the PInDDR bit. Setting Module Name I/O port I/O Port Pin Function PInDDR PIn output 1 PIn input (initial setting) 0 (n = 7 to 0) Note: The output format for PIn is NMOS push-pull. 7.2.19 (1) Port J PJ7, PJ6, PJ5, PJ4, PJ3, PJ2, PJ1, PJ0 The pin function is switched as shown below according to the state of the PJnDDR bit.
Section 7 I/O Ports Table 7.4 Output Specification Signal Name Output Signal Name 7 P17_OE P17 6 P16_OE P16 5 P15_OE P15 4 P14_OE P14 3 P13_OE P13 2 P12_OE P12 1 P11_OE P11 0 P10_OE P10 7 P27_OE P27 6 P26_OE P26 5 P25_OE P25 4 P24_OE P24 3 P23_OE P23 2 P22_OE P22 1 P21_OE P21 0 P20_OE P20 7 SERIRQ_OE SERIRQ FSI.SLCR.FSILIE, 6 P36_OE P36 5 P35_OE P35 LPC.HICR5.SCIFE, HICR4.LPC4E, HICR0.
Section 7 I/O Ports Output Specification Signal Name Output Signal Name PWX1_OE PWX1 PWMX.DACR.OEB = 1 PWMU5B_OE PWMU5B PWMU_B.PWMCONB.PWM5E = 1 PWX0_OE PWX0 PWMX.DACR.OEA = 1 PWMU4B_OE PWMU4B PWMU_B.PWMCONB.PWM4E = 1, PWMU_B.PWMCOND.CNTMD45 = 0 5 PWMU3B_OE PWMU3B PWMU_B.PWMCONB.PWM3E = 1 4 TMO1_OE TMO1 Except TMR_1.TCSR.OS[3:0] = 0000 PWMU2B_OE PWMU2B PWMU_B.PWMCONB.PWM2E = 1, PWMU_B.PWMCOND.CNTMD23 = 0 3 SCK2_OE SCK2 SCI_2.SCR.CKE[1:0] = 01/10/11 + SMR.
Section 7 I/O Ports Port P8 6 Output Specification Signal Name Output Signal Name SCK1_OE SCK1 SCL1_OE SCL1 Signal Selection Register Settings Internal Module Settings SCI_1.SMR.C/A = 1 or SCI_1.SMR.C/A = 0, SCR.CKE[1:0] = 01/10/11 PTCNT1.IIC1AS ICE•IIC1AS•IIC1BS = 1 PTCNT1.IIC1BS 5 P85_OE P85 4 TxD1_OE TxD1 3 P83_OE P83 2 CLKRUN_OE CLKRUN SCI_1.SCR.TE = 1 FSI.SLCR.FSILIE, LPC.HICR5.SCIFE, HICR4.LPC4E, HICR0.
Section 7 I/O Ports Port PB 7 Output Specification Signal Name Output Signal Name RTS_OE RTS Signal Selection Register Settings Internal Module Settings LPC.HICR5.SCIFE, SCIFCR.SCIFOE1, SCIFOE0 SCIFOE = 1: (SCIFE • SCIFOE1 • SCIFOE0 + SCIFE • SCIFOE0) FSISS_OE FSISS FSI.FSICR1.FSIE = 1 6 FSICK_OE FSICK FSI.FSICR1.FSIE = 1 5 DTR_OE DTR LPC.HICR5.SCIFE, SCIFCR.SCIFOE1, SCIFOE0 SCIFOE=1: (SCIFE • SCIFOE1 • SCIFOE0 + SCIFE • SCIFOE0) PC 4 FSIDO_OE FSIDO FSI.FSICR1.
Section 7 I/O Ports Output Specification Signal Name Output Signal Name 7 PD7_OE PD7 6 PD6_OE PD6 5 PD5_OE PD5 4 PD4_OE PD4 3 PD3_OE PD3 2 PD2_OE PD2 1 PD1_OE PD1 0 PD0_OE PD0 7 PWMU5A_OE PWMU5A PWMU_A.PWMCONB.PWM5E = 1 6 PWMU4A_OE PWMU4A PWMU_A.PWMCONB.PWM4E = 1, PWMU_A.PWMCOND.CNTMD45 = 0 5 PWMU3A_OE PWMU3A PWMU_A.PWMCONB.PWM3E = 1 4 PWMU2A_OE PWMU2A PWMU_A.PWMCONB.PWM2E = 1, PWMU_A.PWMCOND.CNTMD23 = 0 3 TMOX_OE TMOX Except TMR_X.TCSR.
Section 7 I/O Ports Output Specification Signal Name Output Signal Name 5 PH5_OE PH5 4 PH4_OE PH4 3 PH3_OE PH3 2 PH2_OE PH2 1 PH1_OE PH1 0 PH0_OE PH0 7 PI7_OE PI7 6 PI6_OE PI6 5 PI5_OE PI5 4 PI4_OE PI4 3 PI3_OE PI3 2 PI2_OE PI2 1 PI1_OE PI1 0 PI0_OE PI0 7 PJ7_OE PJ7 6 PJ6_OE PJ6 5 PJ5_OE PJ5 4 PJ4_OE PJ4 3 PJ3_OE PJ3 2 PJ2_OE PJ2 1 PJ1_OE PJ1 0 PJ0_OE PJ0 Port PH PI PJ Signal Selection Register Settings Internal Module Settings Rev. 2.
Section 7 I/O Ports 7.3 Change of Peripheral Function Pins For the external sub-clock input and IIC input/output, the multi-function I/O ports can be changed. I/O ports that also function as the external interrupt pins are changed by the setting of ISSR16 and ISSR. I/O ports that also function as the external sub-clock input pin are changed by the setting of PTCNT0. For IIC input/output, change the setting of PTCNT1.
Section 7 I/O Ports 7.3.2 Port Control Register 1 (PTCNT1) PTCNT1 selects ports that also function as IIC input/output pins.
Section 7 I/O Ports 7.3.3 Port Control Register 2 (PTCNT2) PTCNT2 selects ports that also function as SCI input/output pins and controls the port specification. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 Reserved R/W The initial value should not be changed.
Section 8 8-Bit PWM Timer (PWMU) Section 8 8-Bit PWM Timer (PWMU) This LSI has two channels of 8-bit PWM timers, A and B (PWMU_A and PWMU_B). Each PWMU outputs 6 PWM waveforms. Each of the PWM channels of a PWMU can operate independently. A PWMU allows long-period PWM outputs for six channels in 8-bit single-pulse mode and for three channels in 16-bit single-pulse mode. In addition, PWM outputs at a high carrier frequency are available in 8-bit pulse division mode.
Section 8 8-Bit PWM Timer (PWMU) Figure 8.1 shows a block diagram of the PWMU.
Section 8 8-Bit PWM Timer (PWMU) 8.2 Input/Output Pins Table 8.1 shows the PWMU pin configuration. Table 8.
Section 8 8-Bit PWM Timer (PWMU) 8.3 Register Descriptions The PWMU has the following registers. Table 8.
Section 8 8-Bit PWM Timer (PWMU) Data Bus Address Width Abbreviation R/W Initial Value Channel B PWM control register A_B (for clock control) PWMCONA_B R/W H'00 H'FD1C 8 PWM control register B_B (for output control) PWMCONB_B R/W H'00 H'FD1D 8 PWM control register C_B (for mode control) PWMCONC_B R/W H'00 H'FD1E 8 PWM control register D_B (for phase control) PWMCOND_B R/W H'00 H'FD1F 8 PWM prescaler register 0_B PWMPRE0_B R/W H'00 H'FD11 8 PWM prescaler register 1_B PWMPRE1
Section 8 8-Bit PWM Timer (PWMU) 8.3.1 PWM Control Register A (PWMCONA) PWMCONA selects the PWM clock source. Initial Value Bit Bit Name 7, 6 CLK1, CLK0 All 0 R/W R/W Description Clock Select 1, 0 These bits select the PWM count clock source. CLK1 CLK0 0 5 to 0 – All 0 R 0: Internal clock φ is selected 0 1: Internal clock φ/2 is selected 1 0: Internal clock φ/4 is selected 1 1: Internal clock φ/8 is selected Reserved These bits are always read as 0 and cannot be modified. 8.3.
Section 8 8-Bit PWM Timer (PWMU) Bit Bit Name Initial Value R/W Description 4 PWM4E 0 R/W PWMU4 Output Enable • 8-bit single-pulse/pulse-division mode 0: PWMU4 output and counter operation are disabled. 1: PWMU4 output and counter operation are enabled. • 16-bit single-pulse mode 0: PWMU4 output and counter operation are disabled. 1: PWMU4 output and counter operation are enabled. 3 PWM3E 0 R/W PWMU3 Output Enable 0: PWMU3 output and counter operation are disabled.
Section 8 8-Bit PWM Timer (PWMU) Bit Bit Name Initial Value R/W Description 0 PWM0E 0 R/W PWMU0 Output Enable • 8-bit single-pulse/pulse division mode 0: PWMU0 output and counter operation are disabled. 1: PWMU0 output and counter operation are enabled. • 16-bit single-pulse mode 0: PWMU0 output and counter operation are disabled. 1: PWMU0 output and counter operation are enabled. Rev. 2.00 Sep.
Section 8 8-Bit PWM Timer (PWMU) 8.3.3 PWM Control Register C (PWMCONC) PWMCONC selects the PWM count mode and operating mode for each channel. Bit Bit Name Initial Value R/W 7 ⎯ 0 R/W Description Reserved The initial value should not be changed. 6 CNTMD01 0 R/W Channels 0 and 1 Counter Select 0: Channels 0 and 1 are in 8-bit counter operation. 1: Channels 0 and 1 are in 16-bit counter operation (Upper: channel 1, lower: channel 0).
Section 8 8-Bit PWM Timer (PWMU) 8.3.4 PWM Control Register D (PWMCOND) PWMCOND selects the PWM count mode and output phase for each channel.
Section 8 8-Bit PWM Timer (PWMU) 8.3.5 PWM Prescaler Registers 0 to 5 (PWMPRE0 to PWMPRE5) PWMPRE are 8-bit readable/writable registers used to set the PWM cycle. The initial value is H'00. When the PWMPRE value is n, the PWM cycle is calculated as follows. (1) 8-Bit Single Pulse Mode PWM cycle = [255 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255) Table 8.
Section 8 8-Bit PWM Timer (PWMU) (2) 16-Bit Single Pulse Mode When 16-bit single pulse mode is selected, PWMPRE0, PWMPRE2, and PWMPRE4 are valid. The settings of PWMPRE1, PWMPRE3, and PWMPRE5 are invalid. PWM cycle = [65535 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255) Table 8.4 Resolution, PWM Conversion Period, and Carrier Frequency (16-Bit Counter Operation) when φ = 20 MHz Carrier Frequency Internal Clock Frequency Resolution PWM Conversion Period Single Pulse Mode Min. Max. Min. Max.
Section 8 8-Bit PWM Timer (PWMU) 8.3.6 PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5) PWMREG0 to PWMREG5 are 8-bit readable/writable registers used to set the high period (duty) of the PWM output pulse. The initial value is H'00. (1) 8-Bit Single Pulse Mode Directly set the high period of the pulse for PWM output. With PWMREG registers, the duty cycle of the PWM output pulse is specified as a value from 0/255 to 255/255 with a resolution of 1/255.
Section 8 8-Bit PWM Timer (PWMU) 8.4 Operation The PWMU operates in 8-bit single pulse mode, 16-bit single pulse mode, or 8-bit division pulse mode. 8.4.1 Single-Pulse Mode (8 Bits, 16 Bits) Figure 8.2 shows a block diagram of 8-bit single pulse mode. Figure 8.3 shows a block diagram of 16-bit single pulse mode. Clock generator PRELAT0 CNT0 Comparator 0 PWMU00 REGLAT0 PRELAT1 CNT1 Comparator 1 PWMU01 REGLAT1 Figure 8.2 Block Diagram of 8-Bit Single Pulse Mode Rev. 2.00 Sep.
Section 8 8-Bit PWM Timer (PWMU) Clock generator PRELAT0 CNT0 Comparator 0 PWMU00 (Output disabled) REGLAT0 PRELAT1 CNT1 Comparator 1 PWMU01 REGLAT1 Figure 8.3 Block Diagram of 16-bit Single Pulse Mode Rev. 2.00 Sep.
Section 8 8-Bit PWM Timer (PWMU) When the PWMnE bit (n = 0 to 5) in PWMCONB is set to 1, the PWMU outputs pulses that start with a high level. The updated PWMREG value is written in REGLAT, and the updated PWMPRE value is written in PRELAT. When the REGLAT value is less than the duty counter value, the PWMU outputs a high level (when direct output is selected). At each PWM clock timing, the duty counter is incremented.
Section 8 8-Bit PWM Timer (PWMU) If the PWMREG value is changed during PWM output, the PWMREG value is loaded into REGLAT when the duty counter overflows (at the beginning of the next PWM cycle). The following shows the PWMU output waveform when the PWMREG value is changed. Duty counter H'FF REGLAT' (value after write) REGLAT H'00 PWMUO PWMREG write signal Figure 8.
Section 8 8-Bit PWM Timer (PWMU) 8.4.2 Pulse Division Mode In pulse division mode, the higher-order four bits in PWMREG specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The following shows the duty cycle of the basic pulse. Table 8.6 Basic Pulse Duty Cycle Upper 4 bits Basic Pulse Waveform (Internal) 0 1 2 3 4 5 6 7 8 9 A B C D E F B'0000 B'0001 B'0010 B'0011 B'0100 B'0101 B'0110 B'0111 B'1000 B'1001 B'1010 B'1011 B'1100 B'1101 B'1110 B'1111 Resolution Rev. 2.
Section 8 8-Bit PWM Timer (PWMU) The lower four bits in PWMREG specify the position of pulses added to the 16 basic pulses. The additional pulse adds a high period (when PHnS = 0) at the resolution width before the rising edge of the basic pulse. Although there is no rising edge of the basic pulse when the upper four bits in PWMREG is B'0000, the timing for adding pulses is the same. Table 8.7 shows the additional pulse positions corresponding to the basic pulses, and figure 8.
Section 8 8-Bit PWM Timer (PWMU) (1) Example of Setting 1 conversion period PWMREG setting example Duty cycle Basic Additional waveform pulses H'7F 127/256 112 pulses 15 pulses H'80 128/256 128 pulses 0 pulse H'81 129/256 128 pulses 1 pulse H'82 130/256 128 pulses 2 pulses 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 : Position of additional pulse A duty cycle of 0/256 to 255/256 is output as a low-ripple waveform by combining basic pulses and additional pulses. Figure 8.
Section 8 8-Bit PWM Timer (PWMU) 8.5 Usage Note 8.5.1 Setting Module Stop Mode The module stop control register can be used to enable or disable PWMU operation. The default setting disables PWMU operation. Clearing the module stop mode enables registers to be accessed. For details, see section 26, Power-Down Modes. 8.5.
Section 8 8-Bit PWM Timer (PWMU) Rev. 2.00 Sep.
Section 9 14-Bit PWM Timer (PWMX) Section 9 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 9.1 Features • Division of pulse into multiple base cycles to reduce ripple • Eight resolution settings The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles.
Section 9 14-Bit PWM Timer (PWMX) 9.2 Input/Output Pins Table 9.1 lists the PWMX (D/A) module input and output pins. Table 9.1 Pin Configuration Pin Name Abbreviation I/O Function PWMX output pin 0 PWX0 Output PWMX output of channel A PWMX output pin 1 PWX1 Output PWMX output of channel B 9.3 Register Descriptions The PWMX (D/A) module has the following registers. The PWMX (D/A) registers are assigned to the same addresses with other registers.
Section 9 14-Bit PWM Timer (PWMX) 9.3.1 PWMX (D/A) Counter (DACNT) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper 2-bit counter.
Section 9 14-Bit PWM Timer (PWMX) 9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. As DACNT is 16 bits, data transfer between the CPU is performed through the temporary register (TEMP). For details, see section 9.4, Bus Master Interface.
Section 9 14-Bit PWM Timer (PWMX) • DADRB Bit Bit Name Initial Value R/W Description 15 DA13 1 R/W D/A Data 13 to 0 14 DA12 1 R/W 13 DA11 1 R/W These bits set a digital value to be converted to an analog value.
Section 9 14-Bit PWM Timer (PWMX) 9.3.3 PWMX (D/A) Control Register (DACR) DACR enables the PWM outputs, and selects the output phase and operating speed. Bit Bit Name Initial Value R/W 7 ⎯ 0 R/W` Description Reserved The initial value should not be changed. 6 PWME 0 R/W PWMX Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H′0003 5 ⎯ 1 R Reserved 4 ⎯ 1 R Always read as 1 and cannot be modified.
Section 9 14-Bit PWM Timer (PWMX) 9.3.4 Peripheral Clock Select Register (PCSR) PCSR and the CKS bit of DACR select the operating speed. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved 6 ⎯ 0 R/W The initial value should not be changed. 5 PWCKXB 0 R/W PWMX clock select 4 PWCKXA 0 R/W These bits select a clock cycle with the CKS bit of DACR of PWMX being 1. See table 9.3. 3 to 1 ⎯ All 0 R/W Reserved The initial value should not be changed.
Section 9 14-Bit PWM Timer (PWMX) 9.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. • Write When the upper byte is written to, the upper-byte write data is stored in TEMP.
Section 9 14-Bit PWM Timer (PWMX) Table 9.4 Reading/Writing to 16-bit Registers Read Write Register Word Byte Word Byte DADRA, DADRB O O O × DACNT O × O × [Legend] O: Enabled access. Word-unit access includes accessing byte sequentially, first upper byte, and then lower byte. ×: The result of the access in the unit cannot be guaranteed.
Section 9 14-Bit PWM Timer (PWMX) (a) Read upper byte CPU [H'AA] Upper byte Module data bus Bus interface TEMP [H'57] DACNTH [H'AA] DACNTL [H'57] (b) Read lower byte CPU [H'57] Lower byte Module data bus Bus interface TEMP [H'57] DACNTH [ ] DACNTL [ ] Figure 9.2 DACNT Access Operation (2) [DACNT → CPU (H'AA57) Reading] Rev. 2.00 Sep.
Section 9 14-Bit PWM Timer (PWMX) 9.5 Operation A PWM waveform like the one shown in figure 9.3 is output from the PWMX pin. DA13 to DA0 in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 9.4 and 9.
Section 9 14-Bit PWM Timer (PWMX) Settings and Operation (Examples when φ = 20 MHz) Table 9.5 PCSR Fixed DADR Bits ResoConver- Bit Data sion TL/TH Accuracy C B A S (μs) CFS Cycle Cycle (OS = 0/OS = 1) (Bits) ⎯ ⎯ ⎯ 0 0.05 0 819.2 Always low/high output 14 3.2 (μs) 1 (μs) 0 0 0 1 0.1 10 12.8 Always low/high output 14 DA13 to 0 = H'0000 to H'003F (Data value) × T 6.4 (μs) 1 1.64 (ms) 0 0 1 1 3.
Section 9 14-Bit PWM Timer (PWMX) PCSR Fixed DADR Bits ResoConversion Bit Data TL/TH Accuracy (Bits) C B A CKS (μs) CFS Cycle Cycle (OS = 0/OS = 1) 0 1 1 1 0 819.2 209.7 Always low/high output (μs) (ms) 12.8 1 14 DA13 to 0 = H'0000 to H'00FF (Data value) × T DA13 to 0 = H'0100 to H'3FFF 10 3276.8 Always low/high output 14 DA13 to 0 = H'0000 to H'003F 0 0 DA13 to 0 = H'0040 to H'3FFF 10 Always low/high output 14 0 0 52.4 ms 0 0 13.1 ms 209.
Section 9 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tL1 tf2 tf255 tL2 tL3 tL255 tf256 tL256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tL1 + tL2 + tL3+ ··· + tL255 + tL256 = TL (a) CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tL1 tf2 tL2 tf63 tL3 tL63 tf64 tL64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tL1 + tL2 + tL3 + ··· + tL63 + tL64 = TL (b) CFS = 1 [base cycle = resolution (T) × 256] Figure 9.4 Output Waveform (OS = 0, DADR corresponds to TL) Rev.
Section 9 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tH1 tf2 tf255 tH2 tH3 tf256 tH255 tH256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tH1 + tH2 + tH3 + ··· + tH255 + tH256 = TH (a) CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tH1 tf2 tf63 tH2 tH3 tf64 tH63 tH64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tH1 + tH2 + tH3 + ··· + tH63 + tH64 = TH (b) CFS = 1 [base cycle = resolution (T) × 256] Figure 9.
Section 9 14-Bit PWM Timer (PWMX) In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in figure 9.7. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of the base pulse duty cycle is 2/256 × (T). Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the location of base pulse No. 63 according to table 9.6. Thus, an additional pulse of 1/256 × (T) is to be added to the base pulse.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
Section 9 14-Bit PWM Timer (PWMX) 9.6 Usage Notes 9.6.1 Module Stop Mode Setting PWMX operation can be enabled or disabled by using the module stop control register. In the initial state, PWMX operation is disabled. Register access is enabled by clearing module stop mode. For details, see section 26, Power-Down Modes. Rev. 2.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively. 10.
Section 10 16-Bit Timer Pulse Unit (TPU) [Legend] TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register Timer I/O control registers (H, L) TIOR (H, L): Timer interrupt enable register TIER: Timer status register TSR: TGR (A, B, C, D): TImer general registers (A, B, C, D) Figure 10.1 Block Diagram of TPU Rev. 2.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 A/D converter trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture Interrupt sources 5 sources 4 sources 4 sources • Compare match or input capture 0A • Compare match or input capture 1A • Compare match or input capture 2A • Compare match or input capture 0B • Compare match or input capture 1B • Compare match or input capture 2B • Compare
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 Input/Output Pins Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Register Descriptions The TPU has the following registers. Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Register Name Abbreviation R/W Initial Value Channel 2 Timer general register A_2 TGRA_2 R/W H'FFFF H'FE78 16 Timer general register B_2 TGRB_2 R/W H'FFFF H'FE7A 16 TSTR R/W H'00 H'FEB0 8 TSYR R/W H'00 H'FEB1 8 Common Timer start register Timer synchro register 10.3.1 Data Bus Address Width Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.6 TPSC2 to TPSC0 (channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on φ 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.2 Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial value R/W Description 7 ⎯ 1 R Reserved 6 ⎯ 1 R These bits are always read as 1 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.9 MD3 to MD0 Bit 3 1 MD3* Bit2 2 MD2* Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × Setting prohibited 1 1 0 1 1 × × [Legend] x: Don't care Notes: 1. MD3 is reserved bit. In a write, it should be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.3 Timer I/O Control Register (TIOR) The TIOR registers control the TGR registers. The TPU has four TIOR registers, two each for channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channel 1 and 2. In channel 0, bit 7 is reserved. It is always read as 0 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W 3 TGFD 0 R/(W)* Input Capture/Output Compare Flag D Description Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W 1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B Description Status flag that indicates the occurrence of TGRB input capture or compare match.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.3.7 Timer General Register (TGR) The TGR registers are 16-bit registers with a dual function as output compare and input capture registers.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7 to 3 ⎯ 0 R/W Reserved The initial value should not be changed.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 Interface to Bus Master 10.4.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read from or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10.2. Internal data bus H Bus master L Module data bus Bus interface TCNTH TCNTL Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Internal data bus H Bus master L Module data bus Bus interface TCR Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TMDR Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TCR TMDR Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] Rev.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5 Operation 10.5.1 Basic Functions Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of freerunning operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Section 10 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
Section 10 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software activation TGF Figure 10.8 Periodic Counter Operation (2) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of setting procedure for waveform output by compare match Figure 10.9 shows an example of the setting procedure for waveform output by compare match.
Section 10 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 10.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
Section 10 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. (a) Example of input capture operation setting procedure Figure 10.12 shows an example of the input capture operation setting procedure.
Section 10 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 10.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation.
Section 10 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 10.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.18 shows the register combinations used in buffer operation. Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (1) Example of Buffer Operation Setting Procedure Figure 10.18 shows an example of the buffer operation setting procedure. Buffer operation Select TGR function [1] Set buffer operation [2] Start count [3] [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (2) Examples of Buffer Operation (a) When TGR is an output compare register Figure 10.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Section 10 16-Bit Timer Pulse Unit (TPU) (b) When TGR is an input capture register Figure 10.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0 % to 100 % duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.19 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 0 TGRA_0 TIOCA0 TGRB_0 TIOCC0 TGRD_0 TIOCC0 TIOCD0 TGRA_1 TIOCA1 TGRB_1 2 TIOCA0 TIOCB0 TGRC_0 1 PWM Mode 2 TIOCA1 TIOCB1 TGRA_2 TIOCA2 TGRB_2 TIOCA2 TIOCB2 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. (1) Example of PWM Mode Setting Procedure Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (2) Examples of PWM Mode Operation Figure 10.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty. TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Section 10 16-Bit Timer Pulse Unit (TPU) (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 10.26 shows an example of phase counting mode 1 operation, and table 10.21 summarizes the TCNT up/down-count conditions.
Section 10 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 10.27 shows an example of phase counting mode 2 operation, and table 10.22 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.27 Example of Phase Counting Mode 2 Operation Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (c) Phase counting mode 3 Figure 10.28 shows an example of phase counting mode 3 operation, and table 10.23 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 10.28 Example of Phase Counting Mode 3 Operation Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 10.29 shows an example of phase counting mode 4 operation, and table 10.24 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 10.29 Example of Phase Counting Mode 4 Operation Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.6 Interrupts 10.6.1 Interrupt Source and Priority There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Section 10 16-Bit Timer Pulse Unit (TPU) (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channel 0, and two each for channels 1 and 2.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.7 Operation Timing 10.7.1 Input/Output Timing (1) TCNT Count Timing Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. φ Internal clock Falling edge Rising edge TCNT input clock N-1 TCNT N N+1 N+2 Figure 10.30 Count Timing in Internal Clock Operation φ External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 10.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 10.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal N TCNT H'0000 N TGR Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (5) Buffer Operation Timing Figures 10.36 and 10.37 show the timing in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 10.36 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 10.37 Buffer Operation Timing (Input Capture) Rev. 2.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.7.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 10.38 TGI Interrupt Timing (Compare Match) (2) TGF Flag Setting Timing in Case of Input Capture Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (3) TCFV Flag/TCFU Flag Setting Timing Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 10.42 shows the timing for status flag clearing by the CPU. TSR write cycle T1 T2 φ Address TSR address Write signal Status flag Interrupt request signal Figure 10.42 Timing for Status Flag Clearing by CPU Rev. 2.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8 Usage Notes 10.8.1 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.3 Conflict between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.44 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address Address Write signal Counter clear signal TCNT N H'0000 Figure 10.44 Conflict between TCNT Write and Clear Operations 10.8.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.5 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10.46 shows the timing in this case. TGR write cycle T1 T2 φ TGR address Address Write signal Compare match signal Prohibited TCNT N N+1 TGR N M TGR write data Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.6 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10.47 shows the timing in this case. TGR write cycle T1 T2 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register N M N TGR Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.8 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.49 shows the timing in this case. TGR write cycle T2 T1 φ Address TGR address Write signal Input capture signal TCNT TGR M M Figure 10.49 Conflict between TGR Write and Input Capture Rev. 2.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.9 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.50 shows the timing in this case. Buffer register write cycle T1 T2 φ Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.10 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.51 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF TCFV Disabled Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.11 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.52 shows the operation timing when there is conflict between TCNT write and overflow. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT TCNT write data H'FFFF M TCFV flag Figure 10.
Section 11 16-Bit Cycle Measurement Timer (TCM) Section 11 16-Bit Cycle Measurement Timer (TCM) This LSI has four channels on-chip 16-bit cycle measurement timers (TCM). Each TCM has a 16bit counter that provides the basis for measuring the periods of input waveforms. 11.
Section 11 16-Bit Cycle Measurement Timer (TCM) Figure 11.1 is a block diagram of the TCM.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.2 Input/Output Pins Table 11.1 lists the input and output pins for the TCMs. Table 11.1 Pin Configuration Channel Pin Name I/O Function 0 TCMCKI0 Input External counter clock input (TCMMCI0) 1 Cycle measurement control input TCMCYI0 Input TCMCKI1 Input (TCMMCI1) 2 TCMCYI1 Input External event input TCMCKI2 Input External counter clock input Cycle measurement control input TCMCYI2 Input TCMCKI3 Input (TCMMCI3) TCMCYI3 11.
Section 11 16-Bit Cycle Measurement Timer (TCM) Channel Register Name Abbreviation R/W Initial Value Channel 1 TCM timer counter_1 TCMCNT_1 R/W H'0000 H'FBD0 16 TCM cycle upper limit register_1 TCMMLCM_1 R/W H'FFFF H'FBD2 16 TCM cycle lower limit register_1 TCMMINCM_1 R/W H'0000 H'FBDC 16 TCM input capture register_1 TCMICR_1 R H'0000 H'FBD4 16 TCM input capture buffer register_1 TCMICRF_1 R H'0000 H'FBD6 16 TCM status register_1 TCMCSR_1 R/W H'00 H'FBD8 8 TCM control register_1 T
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.1 TCM Timer Counter (TCMCNT) TCMCNT is a 16-bit readable/writable up-counter. The input clock is selected by the bits CKS2 to CKS0 in TCMCR. When CKS2 to CKS0 are set to B'111, the external clock is selected. In this case, the rising or falling edge is selected by CKSEG in TCMCR. When TCMCNT overflows (counting changes the value from H'FFFF to H'0000), OVF in TCMCSR is set to 1.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.3 TCM Cycle Lower Limit Register (TCMMINCM) TCMMINCM is a 16-bit readable/writable register. TCMMINCM is available as a cycle lower limit register when the TCMMDS bit in TCMCR is set to 1 (operation is in cycle measurement mode). In cycle measurement mode, a value that sets a lower limit on the measurement period can be set in TCMMINCM.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.6 TCM Status Register (TCMCSR) TCMCSR is an 8-bit readable/writable register that controls operation of the interrupt sources. Bit Bit Name Initial Value R/W 7 OVF 0 R/(W)* Timer Overflow Description This flag indicates that the TCMCNT has overflowed. [Setting condition] Overflow of TCMCNT (change in value from H'FFFF to H'0000) [Clearing condition] Reading OVF when OVF = 1 and then writing 0 to OVF.
Section 11 16-Bit Cycle Measurement Timer (TCM) Bit Bit Name Initial Value R/W 3 ICPF 0 R/(W)* Input Capture Generation Description Timer mode: The flag indicates that the value in TCMCNT has been transferred to TCMICR on generation of an input capture signal. This flag is set when the input capture signal is generated, i.e. on detection of the edge selected by the IEDGD bit on the TCMCYI input pin.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.7 TCM Control Register (TCMCR) TCMCR is an 8-bit readable/writable register. TCMCR selects input capture input edge, counter start, and counter clock, and controls operation mode. Bit Bit Name Initial Value R/W Description 7 CST 0 R/W Counter Start In timer mode, setting this bit to 1 starts counting by TCMCNT; clearing this bit stops counting by TCMCNT. Then, the counter is initialized to H'0000, and input-capture operation stops.
Section 11 16-Bit Cycle Measurement Timer (TCM) Bit Bit Name Initial Value R/W Description 4 IEDG 0 R/W Input Edge Select In timer mode, selects the falling or rising edge of the TCMCYI input for use in input capture, in combination with the value of the POCTL bit. In cycle measurement mode, selects the falling or rising edge of the TCMCYI input for use in measurement, in combination with the value of the POCTL bit.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.8 TCM Interrupt Enable Register (TCMIER) TCMIER is an 8-bit readable/writable register that enables or disables interrupt requests. Bit Bit Name Initial Value R/W Description 7 OVIE 0 R/W Counter Overflow Interrupt Enable Enables or disables the issuing of interrupt requests on setting of the OVF flag in TCMCSR to 1.
Section 11 16-Bit Cycle Measurement Timer (TCM) Bit Bit Name Initial Value R/W Description 2 MINUDIE 0 R/W Cycle Lower Limit Underflow Interrupt Enable Enables or disables the issuing of the TUDI interrupt requests when the MINUDF flag in TCMCSR is set to 1. 0: Disable interrupt requests by MINUDF 1: Enable interrupt requests by MINUDF 1 CMMS 0 R/W Cycle Measurement Mode Selection Selects use of the TCMMCI signal in cycle measurement mode.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.4 Operation The TCM operates in timer mode or cycle measurement mode. TCM is in timer mode after a reset. 11.4.1 Timer Mode When the TCMMDS bit in TCMCR is cleared to 0, TCM operates in timer mode. (1) Counter Operation TCMCNT operates as a free running counter in timer mode. TCMCNT starts counting up when the CST bit in TCMCR is set to 1.
Section 11 16-Bit Cycle Measurement Timer (TCM) (2) Input Capture The value in TCMCNT is transferred to TCMICR by detecting input edge of TCMCYI pin in timer mode. At this time, the ICPF flag in TCMCSR is set. Detection of rising or falling edges is selectable with the setting of the IEDG bit in TCMCR. Figure 11.4 shows an example of the timing of input capture operations and figure 11.5 shows buffer operation of input capture.
Section 11 16-Bit Cycle Measurement Timer (TCM) (3) CMF Set Timing when a Compare Match occurs The CMF flag in TCMCSR is set in the last state where the values in TCMCNT and TCMMLCM match in timer mode. Therefore, a compare match signal is not generated until a further cycle of the TCMCNT input clock is generated after a match between the values in TCMCNT and TCMMLCM. For details, see section 11.6.2, Conflict between TCMMLCM Write and Compare Match. Figure 11.
Section 11 16-Bit Cycle Measurement Timer (TCM) (2) Measuring a Cycle In cycle measurement mode, one cycle of the input waveform for TCM form one measurement cycle. Start by setting TCMMDS = 0 and then set CST = 0, which clears TCMCNT to H'0000. After that, set an upper or lower limit on the measurement cycle in the TCMMLCM/TCMMINCM register. Finally, place the timer in cycle measurement mode by setting the TCMMDS bit in TCMCR to 1. TCMCNT will count cycles of the selected clock.
Section 11 16-Bit Cycle Measurement Timer (TCM) When the CMMS bit in TCMIER is set to 1, cycle measurement is performed only while the TCMMCI signal is high (MCICTL in TCMCSR is 0). Figure 11.9 shows an example of timing in cycle measurement when the CMMS bit is set to 1. φ TCMCYI TCMMCI TCMCNT M TCMICR L 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9AB0 1 2 3 4 5 M H'0006 H'000B H'0007 Figure 11.
Section 11 16-Bit Cycle Measurement Timer (TCM) Cycle measurement stops if MAXOVF/MINUDF is set to 1 while the CPSPE bit in TCMCR is set to 1. Subsequently clearing MAXOVF/MINUDF to 0 restarts cycle measurement. In this case, the external event can be considered to have stopped if a timer overflow is generated before detection of the first edge. Figure 11.11 shows an example of the timing of the external event stopped state (2).
Section 11 16-Bit Cycle Measurement Timer (TCM) (4) Example of Settings for Cycle Measurement Mode Figure 11.12 shows an example of the flow when cycle measurement mode is to be used. Start Initialization Set TCMMDS to 0 [1] Set CST (TCMCR) to 0 [2] Set TCMMLCM [3] Set TCMIPE = 1 [4] Set OVIE and MAXOVIE to 1 [5] Set TCMMDS to 1 [6] OVF = 1? or MAXOVF = 1? Set timer mode. [2] Stop TCMCNT and initialize to H'0000. [3] Set an upper limit on the measurement period.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.5 Interrupt Sources TCM has five interrupt sources: TICI, TCMI, TOVMI, TUDI, and TOVI. Each interrupt source is either enabled or disabled by the corresponding interrupt enable bit in TCMIER and independently transferred to the interrupt controller. Since a single vector address is allocated for each type of interrupt source from all channels, the flags must be used to discriminate between the sources. Table 11.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6 Usage Notes 11.6.1 Conflict between TCMCNT Write and Count-Up Operation When a conflict between TCMCNT write and count-up operation occurs in the second half of the TCMCNT write cycle, TCMCNT is not incremented and writing to TCMCNT takes priority. Figure 11.13 shows the timing of this conflict. T1 T2 φ Internal write signal Internal clock TCMCNT input clock TCMCNT N-1 N N+1 Figure 11.13 Conflict between TCMCNT Write and Count-Up Operation 11.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6.3 Conflict between TCMICR Read and Input Capture When operation is in timer mode and the corresponding input capture signal is detected during reading of TCMICR, the input capture signal is delayed by one system clock (φ). Figure 11.15 shows the timing of this conflict. φ TCMCYI TCMICR read signal Input capture signal TCMCNT TCMICR N-1 N Capture generated M N+1 N+2 N ICPF Figure 11.15 Conflict between TCMICR Read and Input Capture 11.6.
Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6.5 Conflict between Edge Detection in Cycle Measurement Mode and Clearing of TCMMDS Bit in TCMCR If the CST bit in TCMCR is set to 1 in cycle measurement mode, and the TCMMDS bit in TCMCR is cleared, but the selected edge from TCMCYI is detected at the same time, detection of the selected edge will cause the timer to continue to operate in cycle measurement mode.
Section 11 16-Bit Cycle Measurement Timer (TCM) Rev. 2.00 Sep.
Section 12 16-Bit Duty Period Measurement Timer (TDP) Section 12 16-Bit Duty Period Measurement Timer (TDP) This LSI has a three-channel, 16-bit duty period measurement timer (TDP). The TDP uses a 16-bit counter as the basis for measuring input waveforms and the pulse width. 12.
Section 12 16-Bit Duty Period Measurement Timer (TDP) Figure 12.1 shows a block diagram of the TDP.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.2 Input/Output Pins Table 12.1 lists the pin configuration of the TDP. Table 12.
Section 12 16-Bit Duty Period Measurement Timer (TDP) Data Bus Address Width Channel Register Name Abbreviation R/W Initial Value Channel 1 TDP timer counter_1 TDPCNT_1 R/W H'0000 H'FB60 16 TDP pulse width upper limit register_1 TDPWDMX_1 R/W H'FFFF H'FB62 16 TDP pulse width lower limit register_1 TDPWDMN_1 R/W H'0000 H'FB64 16 TDP cycle upper limit register_1 TDPPDMX_1 R/W H'FFFF H'FB66 16 TDP cycle lower limit register_1 TDPPDMN_1 R/W H'0000 H'FB70 16 TDP input capture
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.1 TDP Timer Counter (TDPCNT) TDPCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to CKS0 in TDPCR1. When CKS2 to CKS0 are set to B'111, the external clock is selected. Rising or falling edge is selected by CKSEG in TDPCSR. When TDPCNT overflows (H'FFFF changes to H'0000), the OVF flag in TDPCSR is set to 1. In timer mode, TDPCNT is initialized to H'0000 when the CST bit in TDPCR1 is cleared.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.3 TDP Pulse Width Lower Limit Register (TDPWDMN) TDPWDMN is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1 (cycle measurement mode), TDPWDMN is available as a pulse width lower limit register. In cycle measurement mode, TDPWDMN can be used to set the lower limit value of measurement pulse width.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.6 TDP Input Capture Register (TDPICR) TDPICR is a 16-bit read-only register. In timer mode, the TDPCNT value is transferred to TDPICR on the edge selected by the IEDG bit in TDPCR1, and the ICPF flag in TDPCSR is set to 1. In cycle measurement mode, the TDPCNT value is transferred to TDPICR when the first edge of the measurement period is detected. At the same time, the ICPF flag in TDPCSR is set to 1.
Section 12 16-Bit Duty Period Measurement Timer (TDP) Bit Bit Name Initial Value R/W 5 TWDMNUDF 0 R/(W)* Pulse Width Lower Limit Underflow Description This flag indicates that the waveform pulse width measured in cycle measurement mode is below the lower limit specified in TDPWDMN.
Section 12 16-Bit Duty Period Measurement Timer (TDP) Bit Bit Name Initial Value R/W 2 CMF 0 R/(W)* Description Compare Match Flag (valid only in timer mode) [Setting condition] • When the TDPCNT value matches the TDPWDMX value in timer mode [Clearing condition] • Reading CMF when CMF = 1 and then writing 0 to CMF Note: In cycle measurement mode, even though the TDPCNT value matches the TDPWDMX value, CMF is not set to 1.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.9 TDP Control Register 1 (TDPCR1) TDPCR1 selects the input capture input edge, starts the TDPCNT counter, selects the counter clock, and controls the operating mode. Bit Bit Name Initial Value R/W Description 7 CST 0 R/W Counter Start In timer mode, setting this bit to 1 starts counting by TDPCNT, and clearing it stops counting. After the bit is cleared, the counter is initialized to H'0000, and the inputcapture operation stops.
Section 12 16-Bit Duty Period Measurement Timer (TDP) Bit Bit Name Initial Value R/W Description 4 IEDG 0 R/W Input Edge Select In timer mode, in combination with the value of the POCTL bit, selects the falling or rising edge of the TDPCYI input for capturing input. In cycle measurement mode, this bit does not affect operation.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.10 TDP Control Register 2 (TDPCR2) TDPCR2 selects cycle measurement mode and controls the TDPMCI input polarity. Bit Bit Name Initial Value R/W 7 PMMS 0 R/W Description Cycle Measurement Mode Select Selects whether to use the TDPMCI signal in cycle measurement mode. 0: The TDPMCI signal is not used (cycle measurement is always performed). 1: The TDPMCI signal is used (cycle measurement is performed only while the TDPMCI signal is high).
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.11 TDP Interrupt Enable Register (TDPIER) TDPIER enables or disables interrupt requests and controls whether to enable or disable external event input. Bit Bit Name Initial Value R/W Description 7 OVIE 0 Counter Overflow Interrupt Enable R/W Enables or disables the issuing of OVF interrupt requests when the OVF flag in TDPCSR is set to 1.
Section 12 16-Bit Duty Period Measurement Timer (TDP) Bit Bit Name Initial Value R/W Description 1 TDPIPE 0 Input Capture Input Enable R/W Enables or disables TDPCYI pin input. To use input capture and cycle measurement mode, set this bit to 1. 0: Disabled 1: Enabled Note: Change this bit when CST = 0 and TDPMDS = 0. 0 TPDMNIE 0 R/W Cycle Lower Limit Underflow Interrupt Enable Enables or disables the issuing of TPDMNUDF interrupt requests when the TPDMNUDF flag in TDPCSR is set to 1.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.4 Operation The TDP operates in timer mode or cycle measurement mode. After a reset, the TDP is in timer mode. 12.4.1 Timer Mode When the TDPMDS bit in TDPCR1 is cleared to 0, the TDP operates in timer mode. (1) Counter Operation The TDP operates as a free-running counter in timer mode. The TDP starts counting up when the CST bit in TDPCR1 is set to 1.
Section 12 16-Bit Duty Period Measurement Timer (TDP) (2) Input Capture The value in TDPCNT is transferred to TDPICR by detecting the input edge of the TDPCYI pin in timer mode. At the same time, the ICPF flag in TDPCSR is set. Detection of rising or falling edges is selectable by setting the IEDG bit in TDPCR1. Figure 12.4 shows an example of the timing of input capture operations, and figure 12.5 shows an example of buffer operation for input capture.
Section 12 16-Bit Duty Period Measurement Timer (TDP) (3) CMF Setting Timing when a Compare Match Occurs The CMF flag in TDPCSR is set in the last state in which the values in TDPCNT and TDPWDMX match (timing when TDPCNT updates the matched count value) in timer mode. Accordingly, a compare match signal is not generated until an additional cycle of the TDPCNT input clock is generated after a match between the values in TDPCNT and TDPWDMX. For details, see section 12.6.
Section 12 16-Bit Duty Period Measurement Timer (TDP) (2) Measuring a Cycle In cycle measurement mode, one cycle of the TDP input waveform forms one measurement cycle. Start by setting TDPMDS = 0 and CST = 0, which clears TDPCNT to H'0000. Next, set the upper limit and lower limit values of the measurement pulse width in TDPWDMX and TDPWDMN, and set the upper limit and lower limit values of the measurement cycle in the TDPPDMX and TDPPDMN.
Section 12 16-Bit Duty Period Measurement Timer (TDP) Figure 12.8 shows an example of timing in cycle measurement. φ TDPCYI TDPCNT clear signal TDPCNT input clock TDPCNT M TDPICR L H'0000 H'0001 N-1 N H'0000 M 1 N L M 1 H'0001 TDPWDMX/TDPWDMN/ TDPPDMX/TDPPDMN TDPICRF K Figure 12.8 Example of Timing in Cycle Measurement When the PMMS bit in TDPCR2 is set to 1, cycle measurement is performed only while the TDPMCI signal is high. Figure 12.
Section 12 16-Bit Duty Period Measurement Timer (TDP) (3) Determination of External Event (TDPCYI) Stoppage Stoppage for an external event (TDPCYI) can be determined from the timer overflow flag. There are two types of such stoppage. Stoppage for an external event can be considered to have occurred when the timer overflows within the period from the start of cycle measurement mode to the detection of the first edge (rising or falling, as selected by the POCTL bit in TDPCR1). Figure 12.
Section 12 16-Bit Duty Period Measurement Timer (TDP) (4) Setting Example of Setting Cycle Measurement Mode Figure 12.12 shows an example of a flowchart for using cycle measurement mode. Start Initial setting Set TDPMDS = 0 [1] Set CST = 0 [2] Set TDPWDMX [3] Set TDPIPE = 1 [4] Set OVIE = 1 and TWDMXIE = 1 [5] Set TDPMDS = 1 [6] OVF = 1 or TWDMXOVF = 1? Set timer mode. [2] Stop TDPCNT and initialize it to H'0000. [3] Set pulse width upper limit value. [4] Pin input enabled.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.5 Interrupt Sources The TDP has seven interrupt sources; TICI, TCMI, TWDMXI, TWDMNI, TPDMXI, TPDNMI, and TOVI. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in TDPIER and is independently transferred to the interrupt controller. Table 12.3 lists the interrupt sources in order of priority. Table 12.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.6 Usage Notes 12.6.1 Conflict between TDPCNT Write and Count-Up Operation If a conflict between a TDPCNT write and counting up operation occurs in the second half of the TDPCNT write cycle, writing to TDPCNT takes precedence and TDPCNT is not incremented. Figure 12.13 shows the timing of this conflict. T1 T2 φ Internal write signal Write data M Internal clock TDPCNT input clock TDPCNT N-1 M M+1 Figure 12.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.6.3 Conflict between Input Capture and TDPICR Read When the corresponding input capture signal is detected during reading of TDPICR in timer mode, the input capture signal is delayed by one cycle of the system clock (φ). Figure 12.15 shows the timing of this conflict. φ TDPCYI TDPICR read signal Input capture signal TDPCNT N-1 TDPICR N Capture occurs M N+1 N+2 N ICPF Figure 12.15 Conflict between Input Capture and TDPICR Read 12.6.
Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.6.5 Conflict between Edge Detection in Cycle Measurement Mode and TDPMDS Bit Clearing When the TDPMDS bit in TDPCR1 is cleared in cycle measurement mode while the CST bit in TDPCR1 is 1 and the edge of TDPCYI is detected at the same time, the detected edge signal will cause the timer to continue to operate in cycle measurement mode. The timer enters timer mode when the next edge is detected.
Section 12 16-Bit Duty Period Measurement Timer (TDP) Rev. 2.00 Sep.
Section 13 8-Bit Timer (TMR) Section 13 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, and TMR_X) with four channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.
Section 13 8-Bit Timer (TMR) Figures 13.1 and 13.2 show block diagrams of 8-bit timers. An input capture function is added to TMR_X.
Section 13 8-Bit Timer (TMR) Internal clock sources TMR_X φ, φ/2, φ/4, φ/2048, φ/4096, φ/8192 TMR_Y φ/4, φ/256, φ/2048, φ/4096, φ/8192, φ/16384 TMIY (TMCIY) TMIX (TMCIX) Clock selection Clock X Clock Y Compare-match AX Compare-match AY Overflow X Overflow Y TCORA_Y TCORA_X Comparator A_Y Comparator A_X TCNT_Y TCNT_X Clear Y Compare- match BX TMOY TMIY (TMRIY) TMOX TMIX (TMRIX) Compare-match BY Clear X Comparator B_Y Comparator B_X TCORB_Y TCORB_X Internal bus External clock sources C
Section 13 8-Bit Timer (TMR) 13.2 Input/Output Pins Table 13.1 summarizes the input and output pins of the TMR. Table 13.
Section 13 8-Bit Timer (TMR) 13.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). Table 13.
Section 13 8-Bit Timer (TMR) Channel Abbreviation R/W Initial Value Address Data Bus Width TCNT_X R/W H'00 H'FFF4 8 Time constant register A_X TCORA_X R/W H'FF H'FFF6 8 Time constant register B_X TCORB_X R/W H'FF H'FFF7 8 Timer control register_X TCR_X R/W H'00 H'FFF0 8 Timer control/status register_X TCSR_X R/W H'00 H'FFF1 8 Time constant register TCORC R/W H'FF H'FFF5 8 Input capture register R TICRR R H'00 H'FFF2 8 Input capture register F TICRF R H'00 H'
Section 13 8-Bit Timer (TMR) 13.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 (or TCORA_X and TCORA_Y) comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle.
Section 13 8-Bit Timer (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1.
Section 13 8-Bit Timer (TMR) Table 13.
Section 13 8-Bit Timer (TMR) TCR STCR Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description Common 1 0 1 — — Increments at rising edge of external clock 1 1 0 — — Increments at falling edge of external clock 1 1 1 — — Increments at both rising and falling edges of external clock Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated.
Section 13 8-Bit Timer (TMR) Table 13.
Section 13 8-Bit Timer (TMR) TCR TCRXY Channel CKS2 CKS1 CKS0 CKSX CKSY Description TMR_X 0 0 0 0 — Disables clock input 0 0 1 0 — Increments at φ 0 1 0 0 — Increments at φ/2 0 1 1 0 — Increments at φ/4 1 0 0 0 — Disables clock input 0 0 0 1 — Disables clock input 0 0 1 1 — Increments at φ/2048 0 1 0 1 — Increments at φ/4096 0 1 1 1 — Increments at φ/8192 1 0 0 1 — Increments at compare-match A from TCNT_Y* 1 0 1 x — Increments at ri
Section 13 8-Bit Timer (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output.
Section 13 8-Bit Timer (TMR) Bit Bit Name Initial Value R/W Description 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: Only 0 can be written, for flag clearing.
Section 13 8-Bit Timer (TMR) Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits specify how the TMO1 pin output level is to be changed by compare-match A of TCORA_1 and TCNT_1.
Section 13 8-Bit Timer (TMR) Bit Bit Name Initial Value R/W 5 OVF 0 R/(W)* Timer Overflow Flag Description [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ICF 0 R/(W)* Input Capture Flag [Setting condition] When a rising edge and falling edge is detected in the external reset signal in that order.
Section 13 8-Bit Timer (TMR) • TCSR_Y Bit Bit Name Initial Value R/W 7 CMFB 0 R/(W)* Compare-Match Flag B Description [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_Y overflows f
Section 13 8-Bit Timer (TMR) Bit Bit Name Initial Value R/W Description 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits specify how the TMOY pin output level is to be changed by compare-match A of TCORA_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: 13.3.6 * Only 0 can be written, for flag clearing. Time Constant Register C (TCORC) TCORC is an 8-bit readable/writable register.
Section 13 8-Bit Timer (TMR) 13.3.8 Timer Connection Register I (TCONRI) TCONRI controls the input capture function. Bit Bit Name Initial Value R/W Description 7 to 5 — All 0 R/W Reserved 4 ICST 0 R/W The initial value should not be changed. Input Capture Start Bit TMR_X has input capture registers (TICRR and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit.
Section 13 8-Bit Timer (TMR) Table 13.4 Registers Accessible by TMR_X/TMR_Y TMRX/Y H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 0 TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TCR_X TCSR_X TICRR TICRF TCNT TCORC TCORA_X TCORB_X TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y 1 TMR_Y 13.3.10 Timer XY Control Register (TCRXY) TCRXY selects the TMR_X and TMR_Y output pins and internal clock.
Section 13 8-Bit Timer (TMR) 13.4 Operation 13.4.1 Pulse Output Figure 13.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0, and set the CCLR0 bit in TCR to 1 so that TCNT is cleared according to the compare match of TCORA. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB.
Section 13 8-Bit Timer (TMR) 13.5 Operation Timing 13.5.1 TCNT Count Timing Figure 13.4 shows the TCNT count timing with an internal clock source. Figure 13.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges. The counter will not increment correctly if the pulse width is less than these values.
Section 13 8-Bit Timer (TMR) 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 13.6 shows the timing of CMF flag setting.
Section 13 8-Bit Timer (TMR) 13.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a compare-match. φ Compare-match signal N TCNT H'00 Figure 13.8 Timing of Counter Clear by Compare-Match 13.5.
Section 13 8-Bit Timer (TMR) 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of OVF flag setting. φ TCNT H'FF H'00 Overflow signal OVF Figure 13.10 Timing of OVF Flag Setting Rev. 2.00 Sep.
Section 13 8-Bit Timer (TMR) 13.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available. 13.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with TMR_0 occupying the upper 8 bits and TMR_1 occupying the lower 8 bits.
Section 13 8-Bit Timer (TMR) 13.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY. 13.7.
Section 13 8-Bit Timer (TMR) 13.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF. (1) Input Capture Signal Input Timing Figure 13.11 shows the timing of the input capture operation.
Section 13 8-Bit Timer (TMR) (2) Selection of Input Capture Signal Input TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI. The input capture signal selection is shown in table 13.5. Table 13.5 Input Capture Signal Selection TCONRI Bit 4 ICST Description 0 Input capture function not used 1 TMIX pin input selection Rev. 2.00 Sep.
Section 13 8-Bit Timer (TMR) 13.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 13.6 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. Table 13.
Section 13 8-Bit Timer (TMR) 13.9 Usage Notes 13.9.1 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 13.13, clearing takes priority and the counter write is not performed. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 13.13 Conflict between TCNT Write and Clear 13.9.
Section 13 8-Bit Timer (TMR) 13.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 13.15, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled.
Section 13 8-Bit Timer (TMR) 13.9.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 13.8 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no.
Section 13 8-Bit Timer (TMR) No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high 3 to low level* TCNT Clock Operation Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 N+2 CKS bit rewrite 4 Clock switching from high to high level Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high.
Section 13 8-Bit Timer (TMR) 13.9.6 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. 13.9.7 Module Stop Mode Setting TMR operation can be enabled or disabled using the module stop control register.
Section 13 8-Bit Timer (TMR) Rev. 2.00 Sep.
Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer.
Section 14 Watchdog Timer (WDT) Internal NMI (Interrupt request signal*2) Interrupt control Overflow Clock Clock selection Reset control Internal reset signal*1 TCNT_0 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock Internal bus WOVI0 (Interrupt request signal) TCSR_0 Bus interface Module bus WDT_0 Internal NMI (Interrupt request signal*2) Interrupt control Overflow Clock Clock selection Reset control Internal reset signal*1 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768
Section 14 Watchdog Timer (WDT) 14.2 Input/Output Pins The WDT has the pins listed in table 14.1. Table 14.1 Pin Configuration Name Pin Name I/O Function External sub-clock input pin EXCL Input Inputs the clock pulses to the WDT_1 prescaler counter 14.3 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, see section 14.6.1, Notes on Register Access.
Section 14 Watchdog Timer (WDT) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to 0. 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. • TCSR_0 Bit Bit Name Initial Value R/W 7 OVF 0 R/(W)* Overflow Flag Description Indicates that TCNT has overflowed (changes from H'FF to H'00).
Section 14 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 3 RST/NMI 0 R/W Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The overflow frequency for φ = 20 MHz is enclosed in parentheses. 000: φ/2 (frequency: 25.6 μs) 001: φ/64 (frequency: 819.
Section 14 Watchdog Timer (WDT) • TCSR_1 Bit 7 Bit Name OVF Initial Value 0 R/W Description 1 R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Section 14 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The overflow cycle for φ = 20 MHz and φSUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: φ/2 (frequency: 25.6 μs) 001: φ/64 (frequency: 819.2 μs) 010: φ/128 (frequency: 1.6 ms) 011: φ/512 (frequency: 6.6 ms) 100: φ/2048 (frequency: 26.2 ms) 101: φ/8192 (frequency: 104.
Section 14 Watchdog Timer (WDT) 14.4 Operation 14.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally.
Section 14 Watchdog Timer (WDT) 14.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 14.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF flag of TCSR is set to 1. The timing is shown figure 14.4.
Section 14 Watchdog Timer (WDT) 14.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow Table 14.
Section 14 Watchdog Timer (WDT) 15 8 7 Address : H'FFA8 H'5A 0 Write data 15 8 7 H'A5 Address : H'FFA8 0 Write data Figure 14.5 Writing to TCNT and TCSR (WDT_0) (2) Reading from TCNT and TCSR (Example of WDT_0) These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT. 14.6.
Section 14 Watchdog Timer (WDT) 14.6.3 Changing Values of CKS2 to CKS0 Bits If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of CKS2 to CKS0 bits. 14.6.4 Changing Value of PSS Bit If the PSS bit in TCSR_1 is written to while the WDT is operating, errors could occur in the operation.
Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Section 15 Serial Communication Interface (SCI) Clocked Synchronous Mode: • Data length: 8 bits • Receive error detection: Overrun errors Smart Card Interface: • An error signal can be automatically transmitted on detection of a parity error during reception. • Data can be automatically re-transmitted on detection of an error signal during transmission. • Both direct convention and inverse convention are supported.
Section 15 Serial Communication Interface (SCI) 15.2 Input/Output Pins Table 15.1 shows the input/output pins for each SCI channel. Table 15.
Section 15 Serial Communication Interface (SCI) 15.3 Register Descriptions The SCI has the following registers for each channel. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modes ⎯ normal serial communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections. Table 15.
Section 15 Serial Communication Interface (SCI) 15.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data.
Section 15 Serial Communication Interface (SCI) 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. The CPU can always read SMR. The CPU can write to SMR only at the initial settings; do not have the CPU write to SMR in transmission, reception, and simultaneous data transmission and reception.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 CKS1 0 0 CKS0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the baud rate generator.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 15.7.2, Data Format (Except in Block Transfer Mode).
Section 15 Serial Communication Interface (SCI) 15.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 15.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. The CPU can always read SCR.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W These bits select the clock source and SCK pin function. • Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.
Section 15 Serial Communication Interface (SCI) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 TE 0 R/W 4 RE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled.
Section 15 Serial Communication Interface (SCI) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.
Section 15 Serial Communication Interface (SCI) Bit Bit Name Initial Value R/W Description 4 FER 0 R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked.
Section 15 Serial Communication Interface (SCI) • Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, and TDR can be written to.
Section 15 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial Value 0 R/W Description 1 R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 2 TEND 1 R Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR.
Section 15 Serial Communication Interface (SCI) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 1 R Reserved These bits are always read as 1 and cannot be modified. 3 SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Receive data is stored as LSB first in RDR.
Section 15 Serial Communication Interface (SCI) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.3 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF. The CPU can always read BRR.
Section 15 Serial Communication Interface (SCI) Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 8 Bit Rate (bit/s) n N 9.8304 10 12 Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.
Section 15 Serial Communication Interface (SCI) Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 17.2032 Error (%) 18 19.6608 Bit Rate (bit/s) n N 110 3 75 0.48 3 79 –0.12 3 86 0.31 3 88 –0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.
Section 15 Serial Communication Interface (SCI) Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) φ (MHz) External Input Maximum Bit Clock (MHz) Rate (bit/s) 8 2.0000 125000 14.7456 3.6864 230400 9.8304 2.4576 153600 16 4.0000 250000 10 2.5000 156250 17.2032 4.3008 268800 12 3.0000 187500 18 4.5000 281250 12.288 3.0720 192000 19.6608 4.9152 307200 14 3.5000 218750 20 5.
Section 15 Serial Communication Interface (SCI) Table 15.8 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 10 1.6667 1666666.7 18 3.0000 3000000.0 12 2.0000 2000000.0 20 3.3333 3333333.3 14 2.3333 2333333.3 Table 15.
Section 15 Serial Communication Interface (SCI) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Section 15 Serial Communication Interface (SCI) 15.4.1 Data Transfer Format Table 15.11 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 15.5, Multiprocessor Communication Function. Table 15.
Section 15 Serial Communication Interface (SCI) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Section 15 Serial Communication Interface (SCI) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin.
Section 15 Serial Communication Interface (SCI) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
Section 15 Serial Communication Interface (SCI) 15.4.5 Serial Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 15 Serial Communication Interface (SCI) Initialization [1] Start transmission Read TDRE flag in SSR TDRE = 1 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 15 Serial Communication Interface (SCI) Table 15.12 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception. Table 15.
Section 15 Serial Communication Interface (SCI) Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER ∨ FER ∨ ORER = 1 that the ORER, PER, and FER flags [3] are all cleared to 0.
Section 15 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? Yes No Framing error processing No Clear RE bit in SCR to 0 PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Flowchart (2) Rev. 2.00 Sep.
Section 15 Serial Communication Interface (SCI) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
Section 15 Serial Communication Interface (SCI) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle = receiving station specification (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 15.
Section 15 Serial Communication Interface (SCI) 15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Section 15 Serial Communication Interface (SCI) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.
Section 15 Serial Communication Interface (SCI) Initialization [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [1] Start reception [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
Section 15 Serial Communication Interface (SCI) [5] No Error processing ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? Yes No Framing error processing Clear RE bit in SCR to 0 [6] Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 2.00 Sep.
Section 15 Serial Communication Interface (SCI) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Section 15 Serial Communication Interface (SCI) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
Section 15 Serial Communication Interface (SCI) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 15 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 15.
Section 15 Serial Communication Interface (SCI) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2.
Section 15 Serial Communication Interface (SCI) Initialization [1] Start reception [2] Read ORER flag in SSR Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR No [4] RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received? [5] Yes Clear RE bit in SCR to 0 [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 15 Serial Communication Interface (SCI) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Section 15 Serial Communication Interface (SCI) [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [1] Initialization Start transmission/reception Read TDRE flag in SSR No [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 15 Serial Communication Interface (SCI) 15.7 Smart Card Interface Description The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register. 15.7.1 Sample Connection Figure 15.21 shows a sample connection between the smart card and this LSI.
Section 15 Serial Communication Interface (SCI) 15.7.2 Data Format (Except in Block Transfer Mode) Figure 15.22 shows the data transfer formats in smart card interface mode. • One frame contains 8-bit data and a parity bit in asynchronous mode. • During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame.
Section 15 Serial Communication Interface (SCI) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 15.23. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard.
Section 15 Serial Communication Interface (SCI) 15.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the internal baud rate generator can be used as a communication clock in smart card interface mode. In this mode, the SCI can operate using a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode).
Section 15 Serial Communication Interface (SCI) 15.7.5 Initialization Before starting transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ORER, ERS, and PER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. 4.
Section 15 Serial Communication Interface (SCI) 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 15.28 shows a sample flowchart for transmission.
Section 15 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCR to 0 End Figure 15.28 Sample Transmission Flowchart Rev. 2.00 Sep.
Section 15 Serial Communication Interface (SCI) 15.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 15.29 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1.
Section 15 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0? No Yes Error processing No RDRF = 1? Yes Read data from RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Figure 15.30 Sample Reception Flowchart Rev. 2.00 Sep.
Section 15 Serial Communication Interface (SCI) 15.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 15.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0. CKE0 SCK Specified pulse width Specified pulse width Figure 15.
Section 15 Serial Communication Interface (SCI) (2) At Transition from Smart Card Interface Mode to Software Standby Mode 1. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK pins to the values for the output fixed state in software standby mode. 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3.
Section 15 Serial Communication Interface (SCI) 15.8 Interrupt Sources 15.8.1 Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Section 15 Serial Communication Interface (SCI) 15.8.2 Interrupts in Smart Card Interface Mode Table 15.14 shows the interrupt sources in smart card interface mode. A TEI interrupt request cannot be used in this mode. Table 15.
Section 15 Serial Communication Interface (SCI) 15.9 Usage Notes 15.9.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 26, Power-Down Modes. 15.9.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly.
Section 15 Serial Communication Interface (SCI) 15.9.6 (1) SCI Operations during Mode Transitions Transmission Before making the transition to module stop or software standby, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode is cancelled and then the TE is set to 1 again.
Section 15 Serial Communication Interface (SCI) Transmission end Transmission start Transition to software standby mode Software standby mode cancelled TE bit SCK output pin Port input/output TxD Port output pin input/output High output Start Stop Port input/output SCI TxD output Port High output SCI TxD output Port Figure 15.
Section 15 Serial Communication Interface (SCI) (2) Reception Before making the transition to module stop, software standby or watch mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 15.
Section 15 Serial Communication Interface (SCI) 15.9.7 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 15.40. Low pulse of half a cycle SCK/Port 4. Low pulse output 1. Transmission end Data Bit 6 Bit 7 2. TE = 0 TE 3. C/A = 0 C/A CKE1 CKE0 Figure 15.
Section 15 Serial Communication Interface (SCI) 15.9.8 Note on Writing to Registers in Transmission, Reception, and Simultaneous Transmission and Reception After 1 is set to the TE and RE bits in SCR to start transmission, reception, and simultaneous transmission and reception, do not write to SMR, SCR, BRR, and SDCR. Also, do not overwrite the same value as the register value.
Section 15 Serial Communication Interface (SCI) Rev. 2.00 Sep.
Section 16 CIR Interface Section 16 CIR Interface This LSI incorporates a custom infra-red interface (CIR). The CIR has various functions for receiving the IR signal in NEC format. 16.1 Features • Supports reception of the IR signal in NEC format • Sampling clock selectable Selectable from internal clocks φ, φ/2, and φ/4, and subclock (φ ) SUB • Noise canceling function Input noise can be filtered out by using a maximum of four stages of filters.
Section 16 CIR Interface Module data bus CIRRDR 0 to 17 (18-byte FIFO) HHMAX HHMIN CCR1 HLMAX HLMIN CCR2 DT0MAX DT0MIN CSTR CIRI 4-stage filter SFR RMIN φ φ/2 Baud rate generator DT1MAX DT1MIN RMAX BRR CEIR φ/4 φSUB Reception control Sampling clock RENDI OVEI REPI FREI ABI HEADFI [Legend] SFR: Receive shift register CCR1: Receive control register 1 CCR2: Receive control register 2 CSTR: Receive status register CEIR: Interrupt enable register BRR: Bit rate register CIRRDR0 to 17: Receive
Section 16 CIR Interface 16.2 Input Pins Table 16.1 shows the input pin of the CIR. Table 16.1 Pin Configuration Pin Name Symbol I/O Function CIR input pin CIRI Input CIR receive data input pin 16.3 Register Description Table 16.2 shows the CIR register configuration. Table 16.
Section 16 CIR Interface Register Name Abbreviation R/W Initial Value Address Repeat header minimum low-level period register RMIN R/W H'00 H'FA50 Repeat header maximum low-level period register RMAX R/W H'00 H'FA51 Notes: 1. Before accessing these registers, clear the MSTPA3 bit (bit 3) in MSTPCRA to 0. 2. See the description of each register for details on R/W. 16.3.
Section 16 CIR Interface Bit Bit Name Initial Value R/W Description 3 REPRCVE 0 R/W Receive Enable after Repeat Detection Enables/disables the CIR reception after a repeat detection. 0: The CIR reception is disabled by a repeat detection. 1: The CIR reception is enabled by a repeat detection 2 ⎯ 0 R/W Reserved The initial value should not be changed. 1 CLK1 0 R/W Reference Clock 0 CLK0 0 R/W 00: Internal clock φ 01: Internal clock φ/2 10: Internal clock φ/4 11: subclock φsub 16.3.
Section 16 CIR Interface 16.3.3 Receive Status Register (CSTR) CSTR indicates the data reception state of the CIR. Bit Bit Name Initial Value R/W 7 CIRBUSY 0 R Description CIR Busy Flag Indicates the data receive state of the CIR. [Setting condition] When the CIR starts data reception. [Clearing condition] When the CIR has finished data reception. 6 CIRRDRF 0 R Receive Data Register Full Indicates whether CIRRDR contains a receive data or not. This bit cannot be modified.
Section 16 CIR Interface Bit Bit Name Initial Value R/W Description 3 REND 0 R/W* Reception End Flag [Setting condition] When the CIR has finished data reception. (When a stop is detected.) [Clearing condition] When writing 0 after reading REND = 1. 2 ABF 0 R/W* Abort Flag An internal reset is generated when an abort (transfer format) is detected. [Setting condition] When data other than logic 0 or 1 is detected. [Clearing condition] When writing 0 after reading ABF = 1.
Section 16 CIR Interface 16.3.4 Interrupt Enable Register (CEIR) CEIR consists of the bits that enable/disable various interrupts. Bit Bit Name Initial Value R/W 7, 6 ⎯ All 0 R/W Description Reserved The initial value should not be changed. 5 REPIE 0 R/W Repeat Detection Interrupt Enable 0: REPI interrupt request is disabled. 1: REPI interrupt request is enabled. 4 OVEIE 0 R/W Overrun Error Interrupt Enable 0: OVEI interrupt request is disabled. 1: OVEI interrupt request is enabled.
Section 16 CIR Interface 16.3.5 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the sampling clock signal used for CIR reception. The bit rate for the CIR reception is determined by a combination of the setting value in BRR and the CLK1 and CLK0 bits in CCR1. Bit Bit Name 7 to 0 BRR7 to BRR1 Initial Value R/W Description All 1 R/W Sets the value of the sampling clock.
Section 16 CIR Interface 16.3.6 Receive Data Register 0 to 17 (CIRRDR0 to CIRRDR17) CIRRDR0 to CIRRDR17 are an 18-byte register that stores receive data, totaling to 18 bytes. CIRRDR0 to CIRRDR17 share one byte of the register address. A receive data in CIRRDR should be read after the CIR has finished data reception (CIRBUSY = 0). If CIRRDR is read during the CIR reception (CIRBUSY = 1), an undefined value is read. Initial Value R/W Description H'00 R Stores the CIR receive data.
Section 16 CIR Interface • HHMAX Bit Bit Name Initial Value R/W Description 15 FLT1 0 R/W Number of Stages of Noise Canceler Circuit Select 14 FLT0 0 R/W 00: The noise canceler circuit consists of one stage 01: The noise canceler circuit consists of two stages 10: The noise canceler circuit consists of three stages 11: The noise canceler circuit consists of four stages 13 FLTE 0 R/W Noise Canceler Circuit Enable 0: Disables the noise canceler circuit 1: Enables the noise canceler circuit
Section 16 CIR Interface 16.3.8 Header Minimum/Maximum Low-Level Period Register (HLMIN/HLMAX) HLMIN and HLMAX specify the minimum and maximum low-level period for a header. • HLMIN Bit Bit Name 7 to 0 HLMIN7 to HLMIN0 Initial Value R/W Description H'00 R/W Specifies the minimum low-level period for a header. Initial Value R/W Description H'00 R/W Specifies the maximum low-level period for a header. • HLMAX Bit Bit Name 7 to 0 HLMAX7 to HLMAX0 16.3.
Section 16 CIR Interface 16.3.10 Data Level 0 Minimum/Maximum Period Register (DT0MIN/DT0MAX) DT0MIN and DT0MAX specify the minimum and maximum low/high-level period for logic 0, high-level period for logic 1, and high-level period for a stop/repeat. • DT0MIN Bit Bit Name 7 to 0 DT0MIN7 to DT0MIN0 Initial Value R/W Description H'00 R/W Specifies the minimum low/high-level period for logic 0, high-level period for logic 1, and high-level period for a stop/repeat.
Section 16 CIR Interface 16.4 Operation The communication protocol of the NEC format is shown in figure 16.2. In the NEC format, data consists of a header part, an address part, a command part, and a stop part. The TFM bits in CCR2 can select which data bytes to be stored in CIRRDR: four bytes of the address, address, command, and command, or two bytes of the address and command. The carrier frequency is 38kHz. CIRI Header Address Address Command Command Stop Figure 16.
Section 16 CIR Interface (2) Stop When a low-level period of 9 ms or more is detected after the reception of a command, the CIR stops data reception. This is not defined in the NEC format. Command Stop CIRI C = 0.56 ms A = 9.0 ms D = 1.78 ms C [Legend] A: Low-level period for a stop C: High-level period for logic 0/1, low-level period for logic 0, and high-level period for a stop D: Low-level period for logic 1 Figure 16.
Section 16 CIR Interface 16.4.1 Determination of Signal Type by Low/High-Level Period The signal type is determined by low/high-level period that is specified in the HHMIN, HHMAX, HLMIN, HLMAX, DT1MIN, DT1MAX, DT0MIN, DT0MAX, RMIN, and RMAX registers. Calculating formula for specified time, setting examples of each maximum/minimum value register during the specified time, and use for each register are described as follows. The symbols in table 16.4 correspond to the ones used in the figure 16.
Section 16 CIR Interface Table 16.4 An Example of Signal Type Determination Register Setting Prescribed Time (Error: 30%) Notes Register Setting Symbol Value Name Setting Time Minimum high-level period for a header or repeat header and minimum lowlevel period for a stop HHMIN A H'079 6.34 ms 6.3 ms HHMIN9 to HHMIN0 Maximum high-level period for a header or repeat header and maximum lowlevel period for a stop HHMAX A H'0DF 11.7 ms 11.
Section 16 CIR Interface 16.4.2 Operation of FIFO Register A FIFO structure provides first-in first-out operation. Operation of the FIFO when it receives data three times (byte 0, byte 1, and byte 2 in order) and is then read three times is as shown below. Operation for first reception of data Operation for data reception three times Number of bytes Number of bytes FIFO contents FIFO contents 1 2 3 4 Byte 0 H'00 H'00 H'00 1 2 3 4 Byte 0 Byte 1 Byte 2 H'00 . . . . . . . . . . . .
Section 16 CIR Interface In case of reading more bytes than the number that has been received, (number of received bytes + 1) of data are always read out from the FIFO. Reception of more than 18 bytes by the FIFO structure for this CIR module leads to an overrun. When an overrun occurs, only values up to the 18th byte to have been received are read out in response to the reading of more than 18 bytes. 16.4.
Section 16 CIR Interface 16.5 Noise Canceler Circuit The CIR incorporates a 4-stage noise canceler. The FLTE, FLT, and FLTCK1 and FLTCK0 bits in HHMAX enable/disable the noise canceler circuit, select the number of stages of the noise canceler circuit, and select the division ratio for generating the noise canceler circuit clock, respectively. Figure 16.6 shows a block diagram of the noise canceler circuit. CIR DATA F. F FLTE = 0 CIRI F. F F. F F. F F. F Noise canceler circuit F. F F. F F.
Section 16 CIR Interface Table 16.5 shows sample settings for the noise canceler circuit. Table 16.5 Sample Settings for Noise Canceler Circuit φ CLK1 and CLK0 BRR Setting Setting FLTCK1 and FLTCK0 Setting CIR Number of Stages Width of Sampling of Noise Canceler Noise Clock Circuit Cancellation 10 MHz φ Not divided 12.9 μs H'80 Divided by 2 Divided by 4 Divided by 8 ⎯ φsub H'00 Not divided Divided by 2 Divided by 4 Divided by 8 25.8 μs 51.6 μs 103.2 μs 31.3 μs 62.
Section 16 CIR Interface 16.6 Reset Conditions The range of initialization caused by a system reset, a software reset controlled by the SRES bit in CCR1, or an abort is shown in table 16.6. Table 16.
Section 16 CIR Interface 16.8 (1) Usage Note CIR Register Setting Before starting the CIR reception, set the CIR by following the flow shown in figure 16.7. Start of setting Clear MSTPA3 bit in MSTPCRA to 0. Set CPHS bit in CCR1. Set each register. Clear CSTR flag. Set CEIR. Set CIRE bit in CCR1 to 1. End of setting Figure 16.9 CIR Setting Flow The CPHS bit in CCR1 should be set before starting reception. When the CIRI pin is high in the idle state, set the CPHS bit to 1.
Section 16 CIR Interface (3) Overrun Operation with the NEC format (2 Bytes are Used) When the reception signal format select bits (bits TFM1 and TFM0 in CCR2) are set to the NEC format (2 bytes are used), the OVRF bit in CSTR is set to indicate the overrun on the reception of the 18th byte by the receive data register. However, this does not affect the contents of the 18th– byte data. Rev. 2.00 Sep.
Section 17 Serial Communication Interface with FIFO (SCIF) Section 17 Serial Communication Interface with FIFO (SCIF) This LSI has single-channel serial communication interface with FIFO buffers (SCIF) that supports asynchronous serial communication. The SCIF enables asynchronous serial communication with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART).
Section 17 Serial Communication Interface with FIFO (SCIF) LPC interface FIER FIIR FFCR FLCR FMCR FLSR FMSR FSCR Bus interface Internal data bus Figure 17.1 shows a block diagram of the SCIF.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.2 Input/Output Pins Table 17.1 lists the SCIF input/output pins. Table 17.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3 Register Descriptions The SCIF has the following registers. The register configuration of the SCIF is shown below. Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in MSTPCRB. For details, see table 17.3. For the SCIF address registers H and L (SCIFADRH, SCIFADRL) and serial IRQ control register 4 (SIRQCR4), see section 20, LPC Interface (LPC). Table 17.
Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.3 Register Access SCIFE Bit in HICR5 0 1 Bit 3 in MSTPCRB 0 1 0 1 SCIFCR H8S CPU 2 access* Access disabled H8S CPU 2 access* Access disabled Other than SCIFCR H8S CPU 2 access* Access disabled LPC access* 1 LPC access* 1 Notes: 1. When LPC access is set, writing from the H8S CPU is disabled. The read value is H'FF. 2. When H8S CPU access is set, writing from the LPC is disabled. The read value is H'00. 17.3.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.3 Transmitter Shift Register (FTSR) FTSR is a register that converts parallel data from the FTxD pin to serial data and then transmits the serial data. When one frame transmission of serial data is completed, the next data is transferred from FTHR. The serial data is transmitted from the LSB (bit 0). FTSR cannot be written from the H8S CPU/LPC interface. 17.3.
Section 17 Serial Communication Interface with FIFO (SCIF) • FDLL Bit Bit Name Initial Value R/W Description 7 to 0 Bit 7 to bit 0 All 0 R/W Lower 8 bits of divisor latch Baud rate = (Clock frequency input to baud rate generator) / (16 × divisor value) 17.3.6 Interrupt Enable Register (FIER) FIER is a register that enables or disables interrupts. It is accessible when the DLAB bit in FLCR is 0.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.7 Interrupt Identification Register (FIIR) FIIR consists of bits that identify interrupt sources. For details, see table 17.4. Bit Bit Name Initial Value R/W Description 7 FIFOE1 0 R FIFO Enable 1, 0 6 FIFOE0 0 R These bits indicate the transmit/receive FIFO setting. 00: Transmit/receive FIFOs disabled 11: Transmit/receive FIFOs enabled 5, 4 ⎯ All 0 R Reserved These bits are always read as 0 and cannot be modified.
Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.4 Interrupt Control Function FIIR Setting/Clearing of Interrupt INTID 2 1 0 INTPEND Priority Type of Interrupt Interrupt Source Clearing of Interrupt - 0 0 0 1 ⎯ No interrupt None 0 1 1 0 1 (high) Receive line status Overrun error, FLSR read parity error, framing error, break interrupt 0 1 0 0 2 Receive data ready Receive data remaining, FIFO trigger level FRBR read or receive FIFO is below trigger level.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.8 FIFO Control Register (FFCR) FFCR is a write-only register that controls transmit/receive FIFOs. Bit Bit Name Initial Value R/W Description 7 RCVRTRIG1 0 W Receive FIFO Interrupt Trigger Level 1, 0 6 RCVRTRIG0 0 W These bits set the trigger level of the receive FIFO interrupt. 00: 1 byte 01: 4 bytes 10: 8 bytes 11: 14 bytes 5, 4 – ⎯ ⎯ Reserved These bits cannot be modified.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.9 Line Control Register (FLCR) FLCR sets formats of the transmit/receive data. Bit Bit Name Initial Value R/W Description 7 DLAB 0 R/W Divisor Latch Address FDLL and FDLH are placed at the same addresses as the FRBR/FTHR and FIER addresses. This bit selects which register is to be accessed.
Section 17 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 2 STOP 0 R/W Stop Bit Specifies the stop bit length for data transmission. For data reception, only the first stop bit is checked regardless of the setting. 0: 1 stop bit 1: 1.5 stop bits (data length: 5 bits) or 2 stop bits (data length: 6 to 8 bits) 1 CLS1 0 R/W Character Length Select 1, 0 0 CLS0 0 R/W These bits specify transmit/receive character data length.
Section 17 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 3 OUT2 0 R/W OUT2 • Normal operation Enables or disables the SCIF interrupt. 0: Interrupt disabled 1: Interrupt enabled • Loopback test Internally connected to the DCD input pin. 2 OUT1 0 R/W OUT1 • Normal operation No effect on operation • Loopback test Internally connected to the RI input pin. 1 RTS 0 R/W Request to Send Controls the RTS output.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.11 Line Status Register (FLSR) FLSR is a read-only register that indicates the status information of data transmission. Bit Bit Name Initial Value R/W Description 7 RXFIFOERR 0 Receive FIFO Error R Indicates that at least one data error (parity error, framing error, or break interrupt) has occurred when the FIFO is enabled.
Section 17 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 5 THRE 1 FTHR Empty R Indicates that FTHR is ready to accept new data for transmission. • When the FIFO is enabled 0: Transmit data of one or more bytes remains in the transmit FIFO. [Clearing condition] Transmit data is written to FTHR. 1: No transmit data remains in the transmit FIFO.
Section 17 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 3 FE 0 Framing Error R Indicates that the stop bit of the receive data is invalid. When the FIFO is enabled, this error occurs in any receive data in the FIFO, and this bit is set when the receive data is in the first FIFO buffer. The UART attempts resynchronization after a framing error occurs.
Section 17 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 1 OE 0 Overrun Error R Indicates occurrence of an overrun error. • When the FIFO is disabled When reception of the next data has been completed without the receive data in FRBR having been read, an overrun error occurs and the previous data is lost. • When the FIFO is enabled When the FIFO is full and reception of the next data has been completed, an overrun error occurs.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.12 Modem Status Register (FMSR) FMSR is a read-only register that indicates the status of or a change in the modem control pins. Bit Bit Name Initial Value R/W Description 7 DCD Undefined R Data Carrier Detect 6 RI Undefined R Ring Indicator Indicates the inverted state of the DCD input pin. Indicates the inverted state of the RI input pin. 5 DSR Undefined R Data Set Ready Indicates the inverted state of the DSR input pin.
Section 17 Serial Communication Interface with FIFO (SCIF) Bit Bit Name Initial Value R/W Description 1 DDSR 0 Delta Data Set Ready Indicator R Indicates a change in the DSR input signal after the DDSR bit is read.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.14 SCIF Control Register (SCIFCR) SCIFCR controls SCIF operations, and is accessible only from the CPU. Bit Bit Name Initial Value R/W Description 7 SCIFOE1 0 R/W 6 SCIFOE0 0 R/W These bits enable or disable PORT output of the SCIF. For details, see table 17.5. 5 ⎯ 0 R/W Reserved Do not change the initial value. 4 OUT2LOOP 0 R/W Enables or disables interrupts during a loopback test.
Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.5 SCIF Output Setting Bit 3 in HICR5 0 0 0 0 1 1 1 1 Bit 7 in SCIFCR 0 0 1 1 0 0 1 1 Bit 6 in SCIFCR 0 1 0 1 0 1 0 1 PB7 and PB5 pins PORT PORT SCIF PORT SCIF PORT SCIF PORT P50 pin PORT PORT SCIF SCIF SCIF SCIF SCIF SCIF Note: P51, PB2 to PB4, and PB6 are input to the SCIF even when the outputs on the PB7, PB5, and P50 pins are set to PORT. Rev. 2.00 Sep.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4 Operation 17.4.1 Baud Rate The SCIF includes a baud rate generator and can set the desired baud rate using registers FDLH, FDLL, and the CKSEL bit in SCIFCR. Table 17.6 shows an example of baud rate settings. Table 17.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.2 Operation in Asynchronous Communication Figure 17.2 illustrates the typical format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data (LSB-first: from the least significant bit), a parity bit, and a stop bit (high level). In asynchronous serial communication, the transmission line is usually held high in the mark state (high level).
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.3 (1) Initialization of the SCIF Initialization of the SCIF Use an example of the flowchart in figure 17.3 to initialize the SCIF before transmitting or receiving data. [1] Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR. Set the SCIF input/ output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR. Start initialization Clear module stop Set SCIFCR [1] [2] Set the DLAB bit in FLCR to 1 to enable access to FDLL and FDLH.
Section 17 Serial Communication Interface with FIFO (SCIF) (2) Serial Data Transmission Figure 17.4 shows an example of the data transmission flowchart. Initialization Start transmission Read THRE flag in FLSR THRE = 1? [1] [1] Confirm that the THRE flag in FLSR is 1, and write transmit data to FTHR. When FIFOs are used, write 1-byte to 16-byte transmit data. When the OUT2 bit in FMCR and the ETBEI bit in FIER are set to 1, an FTHR empty interrupt occurs.
Section 17 Serial Communication Interface with FIFO (SCIF) (3) Serial Data Reception Figure 17.5 shows an example of the data reception flowchart. [1] Initialization Confirm that the DR flag in FLSR is 1 to ensure that receive data is in the buffer. When the OUT2 bit in FMCR and the ERBFI bit in FIER are set to 1, a receive data ready interrupt occurs. Start reception [2] Read the RXFIFOERR, BI, FE, PE, and OE flags in FLSR to ensure that no error has occurred.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.4 Data Transmission/Reception with Flow Control The following shows examples of data transmission/reception for flow control using CTS and RTS. (1) Initialization Figure 17.6 shows an example of the initialization flowchart. Start initialization [1] Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR. Set the SCIF input/output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR.
Section 17 Serial Communication Interface with FIFO (SCIF) (2) Data Transmission/Reception Standby Figure 17.7 shows an example of the data transmission/reception standby flowchart. [1] When a receive data ready interrupt occurs, go to the reception flow. Initialization Receive data ready interrupt? Yes [2] When transmit data exists, go to the transmission flow. [1] (Reception flow) No Yes Transmit data exists? [2] No (Transmission flow) Figure 17.
Section 17 Serial Communication Interface with FIFO (SCIF) (3) Data Transmission Figure 17.8 shows an example of the data transmission flowchart. [1] Confirm that the CTS flag in FMSR is 1. Transmission/reception standby [2] Confirm that the THRE flag in FLSR is 1 to ensure that the transmit FIFO is empty. [1] Read CTS flag in FMSR CTS = 1 [3] Write up to 16 bytes of transmit data in the transmit FIFO.
Section 17 Serial Communication Interface with FIFO (SCIF) (4) Suspension of Data Transmission Figure 17.9 shows an example of the data transmission suspension flowchart. Modem status change interrupt [1] Read DCTS flag in FMSR [1] Read the DCTS flag in FMSR in the modem status change interrupt processing routine. If the DCTS flag is set to 1, the transmission suspension processing starts. [2] Suspend data write to the transmit FIFO. DCTS = 1 Yes No [3] Set the XMITFRST bit in FFCR to 1.
Section 17 Serial Communication Interface with FIFO (SCIF) (5) Data Reception Figure 17.10 shows an example of the data reception flowchart. Receive data ready interrupt [1] Read FLSR [2] BI = 1, FE = 1, PE = 1, or OE = 1 Yes No Read receive FIFO Error processing [3] [1] When data is received, a receive data ready interrupt occurs. Go to the data reception flow by using this interrupt trigger. [2] Confirm that the BI, FE, PE, and OE flags in FLSR are all cleared.
Section 17 Serial Communication Interface with FIFO (SCIF) (6) Suspension of Data Reception Figure 17.11 shows an example of the data reception suspension flowchart. Receive FIFO trigger level interrupt [1] Clear RTS bit in FMCR to 0 [2] [1] When data is received at a trigger level higher than the receive FIFO trigger level specified in the initialization flow, a receive FIFO trigger level interrupt occurs. [2] Clear the RTS bit in FMCR to 0.
Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.5 Data Transmission/Reception Through the LPC Interface As shown in table 17.3, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception shown in figures 17.3 to 17.5 to be made from the LPC interface. Table 17.
Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.8 shows the range of initialization of the registers related to data transmission/reception through the LPC interface, making a classification by each mode. Table 17.
Section 17 Serial Communication Interface with FIFO (SCIF) Register System Reset LPC SCIFRST REGRST Reset LPC LPC Shutdown Abort FMCR LOOP BACK, OUT2, OUT1, RTS, DTR Initialized Retained Initialized Initialized Retained Retained FLSR RXFEFOERR, TEMT, THRE, BI, FE, PE, OE, DR Initialized Retained Initialized Initialized Retained Retained FMSR DDCD, TERI, DDSR, DCTS Initialized Retained Initialized Initialized Retained Retained FSCR Bits 7 to 0 Initialized Retained Initialized Initialized R
Section 17 Serial Communication Interface with FIFO (SCIF) 17.5 Interrupt Sources Table 17.9 lists the interrupt sources. A common interrupt vector is assigned to each interrupt source. When the LPC uses the SCIF, the LPC does not request any interrupts to be sent to the H8S CPU. The SERIRQ signal of the LPC interface transmits an interrupt request to the host. Table 17.
Section 18 I2C Bus Interface (IIC) 2 Section 18 I C Bus Interface (IIC) 2 2 This LSI has a three-channel I C bus interface. The I C bus interface conforms to and provides a 2 subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that 2 controls the I C bus differs partly from the Philips configuration, however. 18.
Section 18 I2C Bus Interface (IIC) • Selection of 16 internal clocks (in master mode) • Direct bus drive (SCL/SDA pin) ⎯ Ten pins—P52/SCL0, P97/SDA0, P86/SCL1, P42/SDA1, PG2/SDA2, PG3/SCL2, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB —(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Note: When using this IIC module, make sure to set bits HNDS, FNC1, and FNC0 in ICXR to 1 in the initial settings.
Section 18 I2C Bus Interface (IIC) ICXR * SCL ExSCLA ExSCLB PS Noise canceler ICCR Clock control ICMR Bus state decision circuit * SDA ExSDAA ExSDAB ICSR Arbitration decision circuit ICDRT Output data control circuit ICDRS Internal data bus φ ICDRR Noise canceler Address comparator [Legend] ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register ICXR: I2C bus extended control register SAR: Slave address register SARX: Slave address
Section 18 I2C Bus Interface (IIC) VDD VCC VCC SCL SCL SDA SDA SCL in SDA out (Master) SCL in This LSI SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) 2 SCL in SCL SDA SDA in SCL SDA SCL out (Slave 2) Figure 18.2 I C Bus Interface Connections (Example: This LSI as Master) Rev. 2.00 Sep.
Section 18 I2C Bus Interface (IIC) 18.2 Input/Output Pins 2 Table 18.1 summarizes the input/output pins used by the I C bus interface. One of three pins can be specified as SCL and SDA input/output pin for IIC_0 and IIC_1. Two or more input/output pins should not be specified for one channel. For the method of setting pins, see section 7.3.2, Port Control Register 1 (PTCNT1). Table 18.
Section 18 I2C Bus Interface (IIC) 18.3 Register Descriptions 2 The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR).
Section 18 I2C Bus Interface (IIC) Channel Register Name 2 ICXR_2 R/W H'00 H'FE8C 8 2 ICCR_2 R/W H'01 H'FE88 8 2 ICSR_2 R/W H'00 H'FE89 8 2 I C bus data register_2 ICDR_2 R/W ⎯ H'FE8E 8 Second slave address register_2 Channel 2 I C bus extended control register_2 I C bus control register_2 I C bus status register_2 SARX_2 R/W H'01 H'FE8E 8 I C bus mode register_2 ICMR_2 R/W H'00 H'FE8F 8 Slave address register_2 SAR_2 R/W H'00 H'FE8F 8 ICRES_2 R/W H'0F H'FE8A 8 2
Section 18 I2C Bus Interface (IIC) 18.3.1 2 I C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT).
Section 18 I2C Bus Interface (IIC) 18.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. If the LSI is in slave mode with 2 the I C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0.
Section 18 I2C Bus Interface (IIC) 18.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. If the LSI is in slave 2 mode with the I C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SARX can be accessed only when the ICE bit in ICCR is cleared to 0.
Section 18 I2C Bus Interface (IIC) Table 18.
Section 18 I2C Bus Interface (IIC) 18.3.4 2 I C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB-First/LSB-First Select 0: MSB-first 1: LSB-first 2 Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit 2 This bit is valid only in master mode with the I C bus format.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to B'000 when a start condition is detected.
Section 18 I2C Bus Interface (IIC) 2 Table 18.4 I C Transfer Rate STCR ICMR Bits 5, 6, and 7 Bit 5 Bit 4 Bit 3 IICX CKS2 CKS1 CKS0 Clock φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz 0 0 0 0 φ/28 286 kHz 357 kHz 571 kHz* 714 kHz* 0 0 0 1 φ/40 200 kHz 250 kHz 400 kHz 500 kHz* 0 0 1 0 φ/48 167 kHz 208 kHz 333 kHz 417 kHz* 0 0 1 1 φ/64 125 kHz 156 kHz 250 kHz 313 kHz 0 1 0 0 φ/80 100 kHz 125 kHz 200 kHz 250 kHz 0 1 0 1 φ/100 80.
Section 18 I2C Bus Interface (IIC) 18.3.5 2 I C Bus Control Register (ICCR) 2 ICCR controls the I C bus interface and performs interrupt flag confirmation. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I C Bus Interface Enable 2 2 2 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 5 MST 0 R/W [MST clearing conditions] 4 TRS 0 R/W 1. When 0 is written by software 2 2. When lost in bus contention in I C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1. When 0 is written by software (except for TRS setting condition 3) 2.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 2 BBSY 0 R/W* Bus Busy 0 SCP 1 W Start Condition/Stop Condition Prohibit In master mode: • Writing 0 in BBSY and 0 in SCP: A stop condition is issued • Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued In slave mode: • Writing to the BBSY flag is disabled.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W 1 IRIC 0 R/(W)* I C Bus Interface Interrupt Request Flag Description 2 2 Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See section 18.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value 1 IRIC 0 R/W Description R/(W)* Note: When the slave address does not match and the general call address is not detected (with all flags of AAS, AASX, and ADZ cleared to 0), transmission and reception do not proceed. Thus, the ICDRE and ICDRF flags will not be set. Nor will the IRIC flag. However, even in this case, if STOPIM is 0, the IRIC flag is set by condition 3 above.
Section 18 I2C Bus Interface (IIC) 2 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set.
Section 18 I2C Bus Interface (IIC) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 0↓ 0↓ 1 0 0 — 0 1↑ 0 0 — — — Arbitration lost 1 — 0↓ 0 0 — 0 0 0 0 — — 0↓ Stop condition detected [Legend] 0: 0-state retained 1: 1-state retained —: Previous state retained 0 ↓: Cleared to 0 1 ↑: Set to 1 Rev. 2.00 Sep.
Section 18 I2C Bus Interface (IIC) Table 18.
Section 18 I2C Bus Interface (IIC) 18.3.6 2 I C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 18.5 and 18.6. Bit Bit Name Initial Value 7 ESTP 0 R/(W)* Error Stop Condition Detection Flag 2 This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W 4 AASX 0 R/(W)* Second Slave Address Recognition Flag Description 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W 2 AAS 0 R/(W)* Slave Address Recognition Flag Description 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 0 ACKB 0 R/W Acknowledge Bit Stores acknowledge data. The bit function varies depending on transmit mode and receive mode. Transmit mode: Holds the acknowledge data returned by the receiving device.
Section 18 I2C Bus Interface (IIC) 2 18.3.7 I C Bus Control Initialization Register (ICRES) ICRES controls IIC internal latch clearance. Bit Bit Name Initial Value R/W Description 7 to 5 — All 0 R/W Reserved 4 — 0 R Reserved 3 CLR3 1 W* IIC Clear 3 to 0 2 CLR2 1 W* 1 CLR1 1 W* Controls initialization of the internal state of IIC_0 and IIC_1. (ICRES_0) 0 CLR0 1 W* 00--: Setting prohibited The initial value should not be changed.
Section 18 I2C Bus Interface (IIC) 18.3.8 2 I C Bus Extended Control Register (ICXR) 2 ICXR enables or disables the I C bus interface interrupt generation and handshake control, and indicates the status of receive/transmit operations. Bit Bit Name Initial Value R/W Description 7 STOPIM 0 R/W Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 5 ICDRF 0 R Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] • When data is received successfully and transferred from ICDRS to ICDRR.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 4 ICDRE 0 R Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to.
Section 18 I2C Bus Interface (IIC) Bit Bit Name Initial Value R/W Description 3 ALIE 0 R/W Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. 2 ALSL 0 R/W Arbitration Lost Condition Select Selects the condition under which arbitration is lost.
Section 18 I2C Bus Interface (IIC) 18.4 Operation 2 2 The I C bus interface has an I C bus format and a serial format. 18.4.1 2 I C Bus Data Format 2 The I C bus format is an addressing format with an acknowledge bit. This is shown in figure 18.3. The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 18.4. 2 Figure 18.5 shows the I C bus timing. The symbols used in figures 18.3 to 18.
Section 18 I2C Bus Interface (IIC) SDA SCL S 1–7 8 9 SLA R/W A 1–7 8 DATA 9 1–7 A DATA 8 9 A/A P 2 Figure 18.5 I C Bus Timing 2 Table 18.7 I C Bus Data Format Symbols Legend S Start condition. The master device drives SDA from high to low while SCL is high SLA Slave address. The master device selects the slave device.
Section 18 I2C Bus Interface (IIC) 18.4.2 Initialization Initialize the IIC by the procedure shown in figure 18.6 before starting transmission/reception of data.
Section 18 I2C Bus Interface (IIC) Start Initialize IIC [1] Initialization Read BBSY flag in ICCR No [2] Test the status of the SCL and SDA lines. BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR [3] Select master transmit mode. Set BBSY =1 and SCP = 0 in ICCR [4] Start condition issuance Read IRIC flag in ICCR [5] Wait for a start condition generation No IRIC = 1? Yes Write transmit data in ICDR [6] Set transmit data for the first byte (slave address + R/W).
Section 18 I2C Bus Interface (IIC) The master mode transmission procedure and operations are described below. 1. Initialize the IIC as described in section 18.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3. Set bits MST and TRS to 1 in ICCR to select master transmit mode. 4. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. 5. Then the IRIC and IRTR flags are set to 1.
Section 18 I2C Bus Interface (IIC) 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Section 18 I2C Bus Interface (IIC) Stop condition issuance SCL (master output) 8 9 SDA Bit 0 (master output) Data 1 SDA (slave output) [7] 1 2 3 4 Bit 7 Bit 6 Bit 5 Bit 4 5 6 7 8 Bit 3 Bit 2 Bit 1 Bit 0 9 [10] Data 2 A A ICDRE IRIC IRTR ICDR Data 1 User processing [9] ICDR write Data 2 [9] IRIC clear [12] Set BBSY= 0 and SCP= 0 (Stop condition issuance) [12] IRIC clear [11] ACKB read Figure 18.
Section 18 I2C Bus Interface (IIC) 18.4.4 Master Receive Operation 2 In I C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. Figure 18.
Section 18 I2C Bus Interface (IIC) The master mode reception procedure and operations are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0 to determine the end of reception. Go to step [6] to halt reception operation if the first frame is the last receive data. 2.
Section 18 I2C Bus Interface (IIC) Master receive mode Master transmit mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read SCL (master output) 9 1 2 3 4 5 6 7 8 SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 2 Bit 7 Bit 6 9 [3] Data 1 SDA (master output) Data 2 A IRIC IRTR ICDRF ICDRR Data 1 Undefined value User processing [1] TRS=0 clear [5] ICDR read (Data 1) [4] IRIC clear [2] ICDR read (Dummy read) [1] IRIC clear
Section 18 I2C Bus Interface (IIC) 18.4.5 Slave Receive Operation 2 In I C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address. Figure 18.13 shows the sample flowchart for the operations in slave receive mode.
Section 18 I2C Bus Interface (IIC) Slave receive mode [1] Initialization. Select slave receive mode. Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Clear IRIC flag in ICCR ICDRF = 1? No [2] Read the receive data remaining unread.
Section 18 I2C Bus Interface (IIC) The slave mode reception procedure and operations are described below. 1. Initialize the IIC as described in section 18.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3.
Section 18 I2C Bus Interface (IIC) Start condition generation [7] SCL is fixed low until ICDR is read SCL (Pin waveform) 1 2 3 4 5 6 7 8 9 1 2 SCL (master output) 1 2 3 4 5 6 7 8 9 1 2 SCL (slave output) Bit 7 Bit 6 Bit 5 SDA (master output) SDA (slave output) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slave address Bit 7 Bit 6 R/W Data 1 [6] A Interrupt request occurrence IRIC ICDRF ICDRS Address+R/W ICDRR Address+R/W Undefined value User processing [2] ICDR read [8] IRIC clea
Section 18 I2C Bus Interface (IIC) 18.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 18.16 shows the sample flowchart for the operations in slave transmit mode.
Section 18 I2C Bus Interface (IIC) In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2.
Section 18 I2C Bus Interface (IIC) 6. Clear the IRIC flag to 0. 7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in the ACKB bit to 0. 8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode. 9. Dummy-read ICDR to release SCL on the slave side. 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1.
Section 18 I2C Bus Interface (IIC) 18.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock. Figures 18.18 to 18.20 show the IRIC set timing and SCL control.
Section 18 I2C Bus Interface (IIC) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 2 3 SDA 8 A 1 2 3 IRIC Clear IRIC Clear IRIC User processing (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception. SCL SDA 8 9 1 8 A 1 IRIC User processing Write to ICDR (transmit) Clear IRIC or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception. Figure 18.
Section 18 I2C Bus Interface (IIC) 18.4.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 18.21 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Section 18 I2C Bus Interface (IIC) The following items are not initialized: • Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE and ICDRF flags) • Internal latches used to retain register read information for setting/clearing flags in ICMR, ICCR, and ICSR • The value of the ICMR bit counter (BC2 to BC0) • Generated interrupt sources (interrupt sources transferred to the interrupt controller) (2) Notes on Initialization • Interrupt flags and interrupt sources are not cl
Section 18 I2C Bus Interface (IIC) 18.5 Interrupt Sources The IIC has interrupt source IICI. Table 18.8 shows the interrupt sources and priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the interrupt controller independently. The IIC interrupts are used as on-chip DTC activation sources. Table 18.
Section 18 I2C Bus Interface (IIC) 18.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction 2 to generate a stop condition is issued before the start condition is output to the I C bus, neither condition will be output correctly. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when accessing ICDR.
Section 18 I2C Bus Interface (IIC) 2 4. The I C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high2 speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds 2 the time determined by the input clock of the I C bus interface, the high period of SCL is extended.
Section 18 I2C Bus Interface (IIC) 2 Table 18.11 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] Item tcyc Indication tSCLHO 0.5 tSCLO (–tSr) tSCLLO tBUFO tSTAHO tSTASO 0.5 tSCLO (–tSf) I2C Bus tSr/tSf Influence Specification (Max.) (Min.
Section 18 I2C Bus Interface (IIC) 6. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly.
Section 18 I2C Bus Interface (IIC) Rev. 2.00 Sep.
Section 19 Keyboard Buffer Control Unit (PS2) Section 19 Keyboard Buffer Control Unit (PS2) This LSI has four on-chip keyboard buffer control unit (PS2) channels. The PS2 is provided with functions conforming to the PS/2 interface specifications. Data transfer using the PS2 employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc. Figure 19.1 shows a block diagram of the PS2. 19.
Section 19 Keyboard Buffer Control Unit (PS2) Internal data bus KBBR KBTR KCLK (PS2AC, PS2BC, PS2CC, PS2DC) Control logic KCLKI KBCRH Parity Transmit counter nalue Bus interface KBCR1 KDI Module data bus KD (PS2AD, PS2BD, PS2CD, PS2DD) Transmission start KBCR2 KDO KBCRL KCLKO Register counter value KBI interrupt KCI interrupt KTI interrupt [Legend] KD: KCLK: KBBR: KBCRH: KBCRL: PS2 data I/O pin PS2 clock I/O pin Keyboard data buffer register Keyboard control register H Keyboard control reg
Section 19 Keyboard Buffer Control Unit (PS2) Figure 19.2 shows how the PS2 is connected. Vcc Vcc Keyboard side System side KCLK in KCLK in Clock KCLK out KCLK out KD in KD in Data KD out KD out Keyboard buffer control unit (This LSI) I/F Figure 19.2 PS2 Connection 19.2 Input/Output Pins Table 19.1 lists the input/output pins used by the keyboard buffer control unit. Table 19.
Section 19 Keyboard Buffer Control Unit (PS2) 19.3 Register Descriptions The PS2 has the following registers for each channel. Table 19.
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.1 Keyboard Control Register 1 (KBCR1) KBCR1 controls data transmission and interrupt, selects parity, and detects transmit error. Bit Bit Name Initial Value R/W 7 KBTS 0 R/W Description Transmit Start Selects start of data transmission or disables transmission.
Section 19 Keyboard Buffer Control Unit (PS2) Bit Bit Name Initial Value R/W 2 KCIF 0 R/(W)* First KCLK Falling Interrupt Flag Description Indicates that the first falling edge of KCLK is detected. When KCIE and KCIF are set to 1, requests the CPU an interrupt. 0: [Clearing condition] After reading KCIF = 1, 0 is written 1: [Setting condition] When the first falling edge of KCLK is detected Note that this flag cannot be set when software standby mode or watch mode is cancelled.
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.2 Keyboard Buffer Control Register 2 (KBCR2) KBCR2 is a 4-bit counter which performs counting synchronized with the falling edge of KCLK. Transmit data is synchronized with the transmit counter, and data in the KBTR is sent to the KD (LSB-first). Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 1 R/W Reserved These bits are always read as 1. The initial value should not be changed.
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.3 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer control unit. Bit Bit Name Initial Value R/W Description 7 KBIOE 0 R/W Keyboard In/Out Enable Selects whether or not the keyboard buffer control unit is used.
Section 19 Keyboard Buffer Control Unit (PS2) Bit Bit Name Initial Value R/W 2 KBF 0 R/(W)* Keyboard Buffer Register Full Description Indicates that data reception has been completed and the received data is in KBBR. When both KBIE and KBF are set to1, an interrupt request is sent to the CPU.
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.4 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer control unit pin output. Bit Bit Name Initial Value R/W 7 KBE 0 R/W Description Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled 6 KCLKO 1 R/W Keyboard Clock Out Controls PS2 clock I/O pin output.
Section 19 Keyboard Buffer Control Unit (PS2) Bit Bit Name Initial Value R/W Description 3 RXCR3 0 R Receive Counter 2 RXCR2 0 R 1 RXCR1 0 R 0 RXCR0 0 R These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be modified. The receive counter is initialized by a reset and when 0 is written in KBE. Its value returns to B'0000 after a stop bit is received.
Section 19 Keyboard Buffer Control Unit (PS2) 19.3.5 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. Its value is valid only when KBF = 1. Bit Bit Name Initial Value R/W Description 7 KB7 0 R Keyboard Data 7 to 0 6 KB6 0 R 8-bit read only data. 5 KB5 0 R 4 KB4 0 R Initialized to H'00 by a reset or when KBIOE is cleared to 0. 3 KB3 0 R 2 KB2 0 R 1 KB1 0 R 0 KB0 0 R 19.3.6 Keyboard Buffer Transmit Data Register (KBTR) KBTR stores transmit data.
Section 19 Keyboard Buffer Control Unit (PS2) 19.4 Operation 19.4.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. Value of KD is valid when the KCLK is low. A sample receive processing flowchart is shown in figure 19.3, and the receive timing in figure 19.4.
Section 19 Keyboard Buffer Control Unit (PS2) Receive processing/ error handling KCLK (pin state) 1 KD (pin state) Start bit 2 3 0 9 1 7 10 Flag cleared 11 Parity bit Stop bit KCLK (input) KCLK (output) Automatic I/O inhibit Previous data KB7 to KB0 KB0 KB1 Receive data PER KBS KBF [1] [2] [3] [4] [5] Figure 19.4 Receive Timing Rev. 2.00 Sep.
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit processing flowchart is shown in figure 19.5, and the transmit timing in figure 19.6.
Section 19 Keyboard Buffer Control Unit (PS2) I/O inhibit KCLK (pin state) 1 2 8 9 10 Start bit KD (pin state) 0 1 7 Parity 11 Receive completed Stop bit notification KCLK (input) KCLK (output) KBTE I/O inhibit KTER KBTS [4] [9] [10] [6] [7] [8] [11] [1] to [3] [5] Figure 19.6 Transmit Timing 19.4.3 Receive Abort This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc.
Section 19 Keyboard Buffer Control Unit (PS2) [1] Read KBCRL, and if KBF = 1, perform processing 1. Start [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less than B'1001, write 0 in KCLKO to abort reception. [3] If the value of bits RXCR3 to RXCR0 is B'1001 or greater, wait until stop bit reception is completed, then perform receive data processing, and proceed to the next operation.
Section 19 Keyboard Buffer Control Unit (PS2) Processing 1 Receive operation ends normally [1] [1] On the system side, drive the KCLK pin low, setting the I/O inhibit state. Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted. Figure 19.
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.4 KCLKI and KDI Read Timing Figure 19.9 shows the KCLKI and KDI read timing. T1 T2 φ* Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode. Figure 19.9 KCLKI and KDI Read Timing 19.4.5 KCLKO and KDO Write Timing Figure 19.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states.
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.6 KBF Setting Timing and KCLK Control Figure 19.11 shows the KBF setting timing and the KCLK pin states. φ* KCLK (pin) 11th fall Internal KCLK Falling edge signal RXCR3 to RXCR0 B'1010 B'0000 KBF KCLK (output) Automatic I/O inhibit Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode. Figure 19.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing Rev. 2.00 Sep.
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.7 Receive Timing Figure 19.12 shows the receive timing. φ* KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 N N+1 N+2 Internal KD (KDI) KBBR7 to KBBR0 Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode. Figure 19.12 Receive Counter and KBBR Data Load Timing 19.4.
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.9 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRH to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 19.14 shows the setting method and an example of operation.
Section 19 Keyboard Buffer Control Unit (PS2) 19.4.10 First KCLK Falling Interrupt An interrupt can be generated by detecting the first falling edge of KCLK on reception and transmission. Software standby mode and watch mode can be cancelled by a first KCLK falling interrupt. • Reception When both KBIOE and KBE are set to 1, KCIF is set after the first falling edge of KCLK has been detected. At this time, if KCIE is set to 1, the CPU is requested an interrupt.
Section 19 Keyboard Buffer Control Unit (PS2) • Canceling software standby mode and watch mode Software standby mode and watch mode are cancelled by a first KCLK falling interrupt. In this case, an interrupt is generated at the first KCLK since software standby mode or watch mode has been shifted (figure 19.17). Notes on canceling operation are explained below.
Section 19 Keyboard Buffer Control Unit (PS2) Software standby mode and watch mode Interrupt control block B KCLK Falling edge detection circuit PS2 Interrupt control A Interrupt vector generation circuit Interrupt request to CPU Figure 19.
Section 19 Keyboard Buffer Control Unit (PS2) 1 2 3 KCLK First KCLK falling edge Automatic clear Internal flag Interrupt generated Interrupt accepted (Accepted at any timing) Figure 19.18 Internal Flag of First KCLK Falling Interrupt in Software Standby Mode and Watch Mode Rev. 2.00 Sep.
Section 19 Keyboard Buffer Control Unit (PS2) 19.5 Usage Notes 19.5.1 KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected. If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 19.19 shows the timing of KBIOE setting and KCLK falling edge detection.
Section 19 Keyboard Buffer Control Unit (PS2) 19.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission Figure 19.20 shows the relationship between the KD output by the KDO bit (KBCRL) and by the automatic transmission. Switch to the KD output by the automatic transmission is performed when KBTS is set to 1 and TXCR is not cleared to 0. In this case, the KD output by the KDO bit (KBCRL) is masked.
Section 20 LPC Interface (LPC) Section 20 LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC includes four register sets, each of which comprises data and status registers, control register, the fast Gate A20 logic circuit, and the host interrupt request circuit. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data and one for host interrupt requests.
Section 20 LPC Interface (LPC) Figure 20.1 shows a block diagram of the LPC.
Section 20 LPC Interface (LPC) 20.2 Input/Output Pins Table 20.1 lists the LPC pin configuration. Table 20.
Section 20 LPC Interface (LPC) 20.3 Register Descriptions The LPC has the following registers. Table 20.
Section 20 LPC Interface (LPC) R/W Register Name Initial Data Bus Abbreviation Slave Host Value Address Width Bidirectional data register 0MW TWR0MW R W H'00 H'FE20 8 Bidirectional data register 0SW TWR0SW W R H'00 H'FE20 8 Bidirectional data register 1 TWR1 R/W R/W H'00 H'FE21 8 Bidirectional data register 2 TWR2 R/W R/W H'00 H'FE22 8 Bidirectional data register 3 TWR3 R/W R/W H'00 H'FE23 8 Bidirectional data register 4 TWR4 R/W R/W H'00 H'FE24 8 Bidirectional
Section 20 LPC Interface (LPC) 20.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1) HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits that determine pin output and the internal state of the LPC interface, and status flags that monitor the internal state of the LPC interface. • HICR0 R/W Bit Bit Name Initial Value 7 LPC3E 0 R/W ⎯ LPC Enables 3 to 1 6 LPC2E 0 R/W ⎯ 5 LPC1E 0 R/W ⎯ Enable or disable the LPC interface function.
Section 20 LPC Interface (LPC) Bit Bit Name Initial Value 4 FGA20E 0 R/W Slave Host Description R/W ⎯ Fast Gate A20 Function Enable Enables or disables the fast Gate A20 function. When the fast Gate A20 is disabled, the normal Gate A20 can be implemented by firmware controlling P81 output.
Section 20 LPC Interface (LPC) Bit Bit Name Initial Value 2 PMEE 0 R/W Slave Host Description R/W ⎯ PME Output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor (Vcc) is needed.
Section 20 LPC Interface (LPC) • HICR1 Bit R/W Initial Bit Name Value Slave Host Description 7 LPCBSY 0 R ⎯ LPC Busy Indicates that the LPC interface is processing a transfer cycle.
Section 20 LPC Interface (LPC) Bit R/W Initial Bit Name Value Slave Host Description 5 IRQBSY 0 R ⎯ SERIRQ Busy Indicates that the LPC interface's SERIRQ is engaged in transfer processing.
Section 20 LPC Interface (LPC) Bit R/W Initial Bit Name Value Slave Host Description 3 SDWNB 0 R/W ⎯ LPC Software Shutdown Bit Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 20.4.4, LPC Interface Shutdown Function (LPCPD).
Section 20 LPC Interface (LPC) 20.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3) HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 and the bit 7 in HICR2 monitor the states of the LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset. The states of other bits are decided by the pin states.
Section 20 LPC Interface (LPC) Bit Bit Name Initial Value 4 ABRT 0 R/W Slave Host Description R/(W)* ⎯ LPC Abort Interrupt Flag This bit is a flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs.
Section 20 LPC Interface (LPC) Bit Bit Name Initial Value 1 IBFIE1 0 R/W Slave Host Description R/W ⎯ IDR1 Receive Complete interrupt Enable Enables or disables IBFI1 interrupt to the slave (this LSI). 0: Input data register (IDR1) receive complete interrupt requests disabled 1: Input data register (IDR1) receive complete interrupt requests enabled 0 ERRIE 0 ⎯ R/W Error Interrupt Enable Enables or disables ERRI interrupt to the slave (this LSI).
Section 20 LPC Interface (LPC) 20.3.3 Host Interface Control Register 4 (HICR4) HICR4 enables/disables channel 4 and controls interrupts to the channel 4 of an LPC interface slave (this LSI). Bit Bit Name Initial Value 7 ⎯ 0 R/W Slave Host Description R/W ⎯ Reserved The initial value bit should not be changed. 6 LPC4E 0 R/W ⎯ LPC Enable 4 0: LPC channel 4 is disabled For IDR4, ODR4, and STR4, address (LADR4) match is not occurred.
Section 20 LPC Interface (LPC) 20.3.4 Host Interface Control Register 5 (HICR5) HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts. Bit Bit Name Initial Value 7 OBEIE 0 R/W Slave Host Description R/W ⎯ Output Buffer Empty Interrupt Enable Enables or disables OBEI interrupts (for this LSI).
Section 20 LPC Interface (LPC) 20.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L) LADR1 sets the LPC channel 1 host address. The LADR1 contents must not be changed while channel 1 is operating (while LPC1E is set to 1). • LADR1H R/W Bit Bit Name Initial Value 7 Bit 15 0 R/W ⎯ Channel 1 Address Bits 15 to 8 6 Bit 14 0 R/W ⎯ Set the LPC channel 1 host address.
Section 20 LPC Interface (LPC) • Host select register I/O Address Bits 5 to 3 Bit 2 Bits 1 and 0 Transfer Cycle Host Select Register Bits 15 to 3 in LADR1 0 Bits 1 and 0 in LADR1 I/O write IDR1 write (data) Bits 15 to 3 in LADR1 1 Bits 1 and 0 in LADR1 I/O write IDR1 write (command) Bits 15 to 3 in LADR1 0 Bits 1 and 0 in LADR1 I/O read ODR1 read Bits 15 to 3 in LADR1 1 Bits 1 and 0 in LADR1 I/O read STR1 read Note: 20.3.
Section 20 LPC Interface (LPC) • LADR2L R/W Bit Bit Name Initial Value 7 Bit 7 0 R/W ⎯ Channel 2 Address Bits 7 to 3 6 Bit 6 1 R/W ⎯ Set the LPC channel 2 host address. 5 Bit 5 1 R/W ⎯ 4 Bit 4 0 R/W ⎯ 3 Bit 3 0 R/W ⎯ 2 Bit 2 0 R/W ⎯ Slave Host Description Reserved This bit is ignored when an address match is decided. 1 Bit 1 1 R/W ⎯ Channel 2 Address Bits 1 and 0 0 Bit 0 0 R/W ⎯ Set the LPC channel 2 host address.
Section 20 LPC Interface (LPC) 20.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L) LADR3 sets the LPC channel 3 host address and controls the operation of the bidirectional data registers. The contents of the address fields in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
Section 20 LPC Interface (LPC) When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4 in LADR3 is inverted, and the values of bits 3 to 0 are ignored.
Section 20 LPC Interface (LPC) 20.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L) LADR4 sets the LPC channel 4 host address. The LADR4 contents must not be changed while channel 4 is operating (while LPC4E is set to 1). • LADR4H R/W Bit Bit Name Initial Value Slave Host Description 7 Bit 15 0 R/W ⎯ Channel 4 Address Bits 15 to 8 6 Bit 14 0 R/W ⎯ Set the LPC channel 4 host address.
Section 20 LPC Interface (LPC) • Host select register I/O Address Bits 5 to 3 Bit 2 Bits 1 and 0 Transfer Cycle Host Select Register Bits 15 to 3 in LADR4 0 Bits 1 and 0 in LADR4 I/O write IDR4 write (data) Bits 15 to 3 in LADR4 1 Bits 1 and 0 in LADR4 I/O write IDR4 write (command) Bits 15 to 3 in LADR4 0 Bits 1 and 0 in LADR4 I/O read ODR4 read Bits 15 to 3 in LADR4 1 Bits 1 and 0 in LADR4 I/O read STR4 read Note: * 20.3.
Section 20 LPC Interface (LPC) 20.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave (this LSI) and host. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host and the slave addresses. TWR0MW is a write-only register for the host, and a read-only register for the slave, while TWR0SW is a write-only register for the slave and a readonly register for the host.
Section 20 LPC Interface (LPC) • STR1 R/W Bit Bit Name Initial Value Slave Host Description 7 DBU17 0 R/W R Defined by User 6 DBU16 0 R/W R The user can use these bits as necessary. 5 DBU15 0 R/W R 4 DBU14 0 R/W R 3 C/D1 0 R R Command/Data When the host writes to IDR1, bit 2 of the I/O address is written into this bit to indicate whether IDR1 contains data or a command.
Section 20 LPC Interface (LPC) • STR2 R/W Bit Bit Name Initial Value Slave Host Description 7 DBU27 0 R/W R Defined by User 6 DBU26 0 R/W R The user can use these bits as necessary. 5 DBU25 0 R/W R 4 DBU24 0 R/W R 3 C/D2 0 R R Command/Data When the host writes to IDR2, bit 2 of the I/O address is written into this bit to indicate whether IDR2 contains data or a command.
Section 20 LPC Interface (LPC) • STR3 (TWRE = 1 or SELSTR3 = 0) R/W Bit Bit Name Initial Value Slave Host Description 7 IBF3B 0 R R Bidirectional Data Register Input Buffer Full Flag This is an internal interrupt source to the slave (this LSI).
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 3 C/D3 R 0 R Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data 1: Content of input data register (IDR3) is a command 2 DBU32 0 R/W R Defined by User The user can use this bit as necessary.
Section 20 LPC Interface (LPC) • STR3 (TWRE = 0 and SELSTR3 = 1) R/W Bit Bit Name Initial Value Slave Host Description 7 DBU37 0 R/W R Defined by User 6 DBU36 0 R/W R The user can use these bits as necessary. 5 DBU35 0 R/W R 4 DBU34 0 R/W R 3 C/D3 0 R R Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command.
Section 20 LPC Interface (LPC) • STR4 R/W Bit Bit Name Initial Value Slave Host Description 7 DBU47 0 R/W R Defined by User 6 DBU46 0 R/W R The user can use these bits as necessary. 5 DBU45 0 R/W R 4 DBU44 0 R/W R 3 C/D4 0 R R Command/Data Flag When the host writes to IDR4, bit 2 of the I/O address is written into this bit to indicate whether IDR4 contains data or a command.
Section 20 LPC Interface (LPC) 20.3.13 SERIRQ Control Register 0 (SIRQCR0) SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. R/W Bit Bit Name Initial Value Slave Host Description 7 Q/C 0 R ⎯ Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame).
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 4 SMIE3B 0 R/W ⎯ Host SMI Interrupt Enable 3B Enables or disables an SMI interrupt request when OBF3B is set by a TWR15 write.
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 2 SMIE2 0 R/W ⎯ Host SMI Interrupt Enable 2 Enables or disables an SMI interrupt request when OBF2 is set by an ODR2 write.
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 0 IRQ1E1 0 R/W ⎯ Host IRQ1 Interrupt Enable 1 Enables or disables a host HIRQ1 interrupt request when OBF1 is set by an ODR1 write.
Section 20 LPC Interface (LPC) 20.3.14 SERIRQ Control Register 1 (SIRQCR1) SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. R/W Bit Bit Name Initial Value Slave Host Description 7 IRQ11E3 0 R/W ⎯ Host IRQ11 Interrupt Enable 3 Enables or disables an HIRQ11 interrupt request when OBF3A is set by an ODR3 write.
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 5 IRQ9E3 0 R/W ⎯ Host IRQ9 Interrupt Enable 3 Enables or disables an HIRQ9 interrupt request when OBF3A is set by an ODR3 write.
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 3 IRQ11E2 0 R/W ⎯ Host IRQ11 Interrupt Enable 2 Enables or disables an HIRQ11 interrupt request when OBF2 is set by an ODR2 write.
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 IRQ9E2 0 R/W ⎯ Host IRQ9 Interrupt Enable 2 Enables or disables an HIRQ9 interrupt request when OBF2 is set by an ODR2 write.
Section 20 LPC Interface (LPC) 20.3.15 SERIRQ Control Register 2 (SIRQCR2) SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host interrupt request outputs. R/W Bit Bit Name Initial Value Slave Host Description 7 IEDIR3 0 R/W ⎯ Interrupt Enable Direct Mode 3 Selects whether an SERIRQ interrupt generation of LPC channel 3 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable bit.
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 5 IRQ11E4 0 R/W ⎯ Host IRQ11 Interrupt Enable 4 Enables or disables an HIRQ11 interrupt request when OBF4 is set by an ODR4 write.
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 3 IRQ9E4 0 R/W ⎯ Host IRQ9 Interrupt Enable 4 Enables or disables an HIRQ9 interrupt request when OBF4 is set by an ODR4 write.
Section 20 LPC Interface (LPC) R/W Bit Bit Name Initial Value Slave Host Description 1 SMIE4 0 ⎯ R/W Host SMI Interrupt Enable 4 Enables or disables an SMI interrupt request when OBF4 is set by an ODR4 write.
Section 20 LPC Interface (LPC) 20.3.17 SERIRQ Control Register 4 (SIRQCR4) SIRQCR4 is used to select the SERIRQ interrupt requests of the SCIF. R/W Initial Value Slave Host Description 7 to 4 ⎯ All 0 R/W ⎯ 3 SCSIRQ3 0 R/W ⎯ SCIF SERIRQ Request 2 SCSIRQ2 0 R/W ⎯ These bits select host interrupt requests of the SCIF. 1 SCSIRQ1 0 R/W ⎯ 0000: No host interrupt request 0 SCSIRQ0 0 R/W ⎯ 0001: HIRQ1 Bit Bit Name Reserved The initial value should not be changed.
Section 20 LPC Interface (LPC) 20.3.18 SCIF Address Register (SCIFADRH, SCIFADRL) SCIFADR sets the host addresses of the SCIF. Do not change the contents of SCIFADR during operation of the SCIF (i.e. while SCIFE is set to 1). • SCIFADRH R/W Bit Bit Name Initial Value 7 ⎯ 0 R/W ⎯ SCIF Addresses 15 to 8 6 ⎯ 0 R/W ⎯ These bits set the host addresses of the SCIF.
Section 20 LPC Interface (LPC) 20.3.19 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt request signal of each frame. Bit Bit Name Initial Value 7 SELSTR3 0 R/W Slave Host Description R/W ⎯ Status Register 3 Selection Selects the function of bits 7 to 4 in STR3 in combination with the TWRE bit in LADR3L. For details of STR3, see section 20.3.12, Status Registers 1 to 4 (STR1 to STR4).
Section 20 LPC Interface (LPC) 20.4 Operation 20.4.1 LPC interface Activation The LPC interface is activated by setting one of the following bits to 1: LPC3E to LPC1E in HICR0 and LPC4E in HICR4. When the LPC interface is activated, the related I/O ports (P37 to P30, P83 and P82) function as dedicated LPC interface input/output pins. In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (P81, P80, PB0, and PB1) to the LPC interface's input/output pins.
Section 20 LPC Interface (LPC) 20.4.2 LPC I/O Cycles There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, bus master I/O write, FW memory read, and FW memory write. Of these, the LPC of this LSI supports I/O read and I/O write. An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state.
Section 20 LPC Interface (LPC) Table 20.
Section 20 LPC Interface (LPC) LCLK LFRAME LAD3 to LAD0 Start ADDR TAR Sync Data TAR Start Cycle type, direction, and size Number of clocks 1 1 4 2 1 2 2 1 Figure 20.2 Typical LFRAME Timing LCLK LFRAME LAD3 to LAD0 Start ADDR Cycle type, direction, and size TAR Sync Slave must stop driving Master will drive high Too many Syncs cause timeout Figure 20.3 Abort Mechanism Rev. 2.00 Sep.
Section 20 LPC Interface (LPC) 20.4.3 Gate A20 The Gate A20 signal can mask address A20 to emulate the address mode of the 8086* architecture CPU used in personal computers. Normally, the Gate A20 signal can be controlled by a firmware. The fast Gate A20 function that realizes high-seed performance by hardware is enabled by setting the FGA20E bit to 1 in HICR0. Note: An Intel microprocessor (1) Regular Gate A20 Operation Output of the Gate A20 signal can be controlled by an H'D1 command and data.
Section 20 LPC Interface (LPC) Table 20.4 GA20 Setting/Clearing Timing Pin Name Setting Condition Clearing Condition GA20 When bit 1 of the data that follows an H'D1 host command is 1 When bit 1 of the data that follows an H'D1 host command is 0 Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to the bit of GA20 in DR Figure 20.4 GA20 Output Rev. 2.00 Sep.
Section 20 LPC Interface (LPC) Table 20.
Section 20 LPC Interface (LPC) 20.4.4 LPC Interface Shutdown Function (LPCPD) The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the LPC software shutdown state is controlled by the SDWNB bit.
Section 20 LPC Interface (LPC) Table 20.6 shows the scope of the LPC interface pin shutdown. Table 20.
Section 20 LPC Interface (LPC) Table 20.
Section 20 LPC Interface (LPC) Figure 20.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3 to LAD0 LFRAME At least 30 µs At least 100 µs At least 60 µs LRESET Figure 20.5 Power-Down State Termination Timing Rev. 2.00 Sep.
Section 20 LPC Interface (LPC) 20.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 20.6.
Section 20 LPC Interface (LPC) Table 20.
Section 20 LPC Interface (LPC) There are two modes⎯continuous mode and quiet mode⎯for serialized interrupts. The mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet mode, the slave with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host.
Section 20 LPC Interface (LPC) 20.5 Interrupt Sources 20.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI The host has six interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, IBF4, OBEI, and ERRI. IBFI1, IBFI2, IBFI3, and IBFI4 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort.
Section 20 LPC Interface (LPC) 20.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15 The LPC interface can request 15 kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1 and the SCIF, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can be requested from LPC channel 2, 3, 4 or SCIF. HIRQ3, HIRQ4, HIRQ5, HIRQ7, HIRQ8, HIRQ13, HIRQ14, and HIRQ15 are only for the SCIF.
Section 20 LPC Interface (LPC) Table 20.
Section 20 LPC Interface (LPC) Table 20.11 HIRQ Setting and Clearing Conditions when SCIF Channels are Used Host Interrupt Setting Condition Clearing Condition HIRQi (i = 1 to 15) Internal CPU sets the corresponding SERIRQ host interrupt request for the SCIF in SIRQCR4 (for details, see the description of SIRQCR4). Reads FMSR and clears the DDCD bit in FMSR Changes in the SCIF input signal DCD are detected.
Section 20 LPC Interface (LPC) 20.6 Usage Note 20.6.1 Data Conflict The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data conflict. For example, if the host and slave both try to access IDR or ODR at the same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to data for which writing has finished.
Section 20 LPC Interface (LPC) Table 20.
Section 20 LPC Interface (LPC) Rev. 2.00 Sep.
Section 21 FSI Interface Section 21 FSI Interface This LSI incorporates the SPI flash memory serial interface (FSI) that supports the communication between this LSI and SPI flash memory. The FSI performs communications using the LPC or CPU of this LSI as a master. 21.1 Features Figure 21.1 shows a block diagram of the FSI. • Supports communications between this LSI and SPI flash memory. • Can operate as a master. • Transfer clock selectable from system clock φ or LCLK.
Section 21 FSI Interface FSICMDI, FSIWI FSITEI, FSIRXI FSICR1/2 SLCR FSIHBARH/L FSISR LCLK LAD 3 to 0 LFRAME FSIBNR FSIINS FS FSIRDINS FSISTR FSIPPINS Address-Change FSISS Trans/Rev Controller LPC I/F CMDHBRH/L FSICK FSILSTR1/2 FSIGPR1 to F FSIARLH/M/L FSIWDHH/HL/LH/LL FSICMDR FSITDR 0 to 7 FSIRDR FSISFR FSIDO FSIDI [Legend] FSISFR: FSI shift register Figure 21.1 FSI Block Diagram Rev. 2.00 Sep.
Section 21 FSI Interface 21.2 Input/Output Pins Table 21.1 shows the input/output pins of the FSI. Table 21.1 Pin Configuration Pin Name Symbol I/O Function FSI slave select FSISS Output FSI slave select signal FSI clock FSICK Output FSI clock signal FSI master data input FSIDI Input FSI data input signal FSI master data output FSIDO Output FSI address/direction/data output signal For details on the input/output pins of the LPC interface, see section 20.2, Input/Output Pins. Table 21.
Section 21 FSI Interface 21.3 Register Description The FSI consists of the following registers. Table 21.
Section 21 FSI Interface R/W Register Name Abbreviation EC Host Initial Value Address FSI general-purpose register 1 FSIGPR1 R/W R H'00 H'FC57 FSI general-purpose register 2 FSIGPR2 R/W R H'00 H'FC58 FSI general-purpose register 3 FSIGPR3 R/W R H'00 H'FC59 FSI general-purpose register 4 FSIGPR4 R/W R H'00 H'FC5A FSI general-purpose register 5 FSIGPR5 R/W R H'00 H'FC5B FSI general-purpose register 6 FSIGPR6 R/W R H'00 H'FC5C FSI general-purpose register 7 FSIGPR7
Section 21 FSI Interface 21.3.1 FSI Control Register 1 (FSICR1) The FSICR1 control bits are classified into three functionalities: resetting the FSI internal signals, enabling/disabling FSI functions, and selecting FSI functions. Bit Bit Name Initial Value 7 SRES 0 R/W EC Host Description R/W ⎯ Software Reset Controls initialization of the FSI internal sequencer. 0: Normal state 1: Clears the internal sequencer.
Section 21 FSI Interface R/W Bit Bit Name Initial Value 3 CPHS 0 R/W ⎯ CPHS: Selects the polarity of the FSICK clock. 2 CPOS 0 R/W ⎯ CPOS: Selects the phase of the FSICK clock. EC Host Description CPHS CPOS 0 0 Initial value of FSICK: Low level Data changes at the FSICK falling edge. 1 1 Initial value of FSICK: High level Data changes at the FSICK falling edge. 1 ⎯ 0 R/W ⎯ 0 1 Setting prohibited 1 0 Setting prohibited Reserved The initial value should not be modified.
Section 21 FSI Interface 21.3.2 FSI Control Register 2 (FSICR2) The FSICR2 control bits are classified into two functionalities: enabling/disabling the FSI communications and enabling/disabling the FSI internal interrupts. Bit Bit Name Initial Value 7 TE 0 R/W EC Host Description R/W ⎯ FSI Transmit Enable Controls FSI transmission and indicates transmission status in combination with the LFBUSY bit. 0: FSI transmission wait state [Clearing condition] When FSI data transmission is completed.
Section 21 FSI Interface 21.3.3 FSI Byte Count Register (FSIBNR) The FSIBNR sets the number of bytes to be transmitted or received by the FSI. This register should not be set in the processing other than FSICMDI and FSIWI interrupt processing. R/W Initial Value EC Host Description 7 to 4 TBN3 0 R/W ⎯ TBN2 0 TBN1 0 TBN0 0 Bit Bit Name Transmit Byte Count 3-0 These bits specify the number of data bytes to be transmitted.
Section 21 FSI Interface R/W Initial Value EC Host Description 2 to 0 RBN2 0 R/W ⎯ RBN1 0 RBN0 0 Bit Bit Name Receive Byte Count 2-0 These bits specify the number of data bytes to be received. After the FSI reception operation ends (when FSIRXI in FSISTR is 1), the RBN value is decremented (−1) each time FSIRDR is read. When all the data bytes have been received, RBN is cleared to B'000.
Section 21 FSI Interface 21.3.5 FSI Instruction Register (FSIRDINS) FSIRDINS sets a read operation instruction to be sent to FSITDR during read operation. When LFBUSY is set to 1, a write to this register by the EC (this LSI) is invalid. This register should be modified during initialization. Bit Initial Value Bit Name 7 to 0 bit 7 to bit 0 All 0 21.3.6 R/W EC Host Description R/W ⎯ These bits store a read operation instruction.
Section 21 FSI Interface Bit Bit Name Initial Value 6 OBF 0 R/W EC Host Description R ⎯ Transmit Data Register Full Indicates whether or not there is data to be written by the EC (this LSI). 0: There is no write data. [Clearing condition] When write data transmission to the SPI flash memory is completed. 1: There is write data. [Setting condition] When the TE bit is set to 1.
Section 21 FSI Interface 21.3.8 FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7) FSITDR stores a total of 8 bytes of transmit data. A total of 8 bytes of addresses, instructions, and data items can be transferred continuously from FSITDR0 through FSITDR7 in this order to the SPI flash memory. When LFBUSY is set to 1, a write to this register by the EC (this LSI) is invalid. This register should not be set in the processing other than FSICMDI and FSIWI interrupt processing.
Section 21 FSI Interface 21.3.10 FSI Access Host Base Address Registers H and L (FSIHBARH and FSIHBARL) FSIHBARH and FSIHBARL store the upper 16 bits of the host start address which is necessary to convert the host address to the SPI flash memory address. The input range of the host address will be determined based on the host start address set in these registers and the memory size set in FSISR. If a host address to be input is out of the determined range, Sync will not be returned.
Section 21 FSI Interface R/W Initial Value EC Host Description 7 to 2 ⎯ All 0 R/W ⎯ 1 FSIMS1 0 R/W ⎯ These bits specify the SPI flash memory size. 0 FSIMS0 0 R/W ⎯ 00: 1 MB Bit Bit Name Reserved The initial value should not be changed. 01: 2 MB 10: 4 MB 11: 8 MB 21.3.12 FSI Command Host Base Address Registers H and L (CMDHBARH and CMDHBARL) CMDHBARH and CMDHBARL set the upper 16 bits of the host start address which is necessary to set a command address.
Section 21 FSI Interface 21.3.13 FSI Command Register (FSICMDR) FSICMDR stores command data during FSI command reception. FSICMDR stores command data when the FSICMDI bit in FSILSTR1 is cleared to 0. It does not store command data when the FSICMDI bit is set to 1. Bit Bit Name Initial Value 7 to 0 bit 7 to bit 0 All 0 R/W EC Host Description R ⎯ These bits store an FSI command. 21.3.14 FSI LPC Command Status Register 1 (FSILSTR1) FSILSTR1 indicates the LPC internal status.
Section 21 FSI Interface Bit Bit Name Initial Value 5 FSIDMYE 0 R/W EC Host Description R/W R FSI Dummy Enable 0: Disables FSI dummy. 1: Enables FSI dummy. 4 FSIWBUSY 0 R/W* R FSI Write Busy Flag 0: FSI write transfer is completed. [Clearing condition] • When this bit is read as 1 and then written with 0. 1: FSI write in transferring [Setting condition] • 3 FSIWI 0 R/W* R SPI flash memory write is received when FLDCT=0. FSI Write Interrupt Flag 0: FSI write interrupt is completed.
Section 21 FSI Interface 21.3.15 FSI LPC Command Status Register 2 (FSILSTR2) FSILSTR2 indicates the LPC internal status. Bit Bit Name 7 to 5 ⎯ R/W Initial Value EC Host Description All 0 R/W ⎯ Reserved The initial value should not be modified. 4 FSIDWBUSY 0 R ⎯ FSI Direct Write Busy Flag Indicates a FSI write transfer status during LPCSPI direct transfer. 0: FSI write transfer is completed.
Section 21 FSI Interface 21.3.16 FSI General-Purpose Registers 1 to F (FSIGPR1 to FSIGPRF) FSIGPR1 to FSIGPRF store data such as the result of FSI command interrupt processing. • FSIGPR1 to FSIGPRF Bit Bit Name Initial Value 7 to 0 bit 7 to bit 0 All 0 R/W EC Host Description R/W R These bits store results of FSI command interrupt processing. 21.3.
Section 21 FSI Interface Bit Bit Name Initial Value 4 FLDCT 0 R/W EC Host Description R/W ⎯ FSI LPC Direct Selects access mode in SPI flash memory write. For details, see section 21.4.6, SPI Flash Memory Write Operation Mode. 0: LPC-SPI indirect transfer 1: LPC-SPI direct transfer 3 FLWAIT 0 R/W ⎯ FSI LPC Wait Selects access mode in SPI flash memory write. For details, see section 21.4.6, SPI Flash Memory Write Operation Mode. 0: No wait cycle is inserted. 1: Wait cycles can be inserted.
Section 21 FSI Interface • FSIARL Bit Bit Name Initial Value 7 to 0 bit 7 to bit 0 All 0 R/W EC Host Description R ⎯ These bits store bits [7:0] of the SPI flash memory address. 21.3.19 FSI Write Data Registers HH, HL, LH, and LL (FSIWDRHH, FSIWDRHL, FSIWDRLH, and FSIWDRLL) FSIWDR stores data to be written to the SPI flash memory. If the host address matches FSIHBAR during LPC/FW memory write cycle, the FSIWDR value will be updated. FSIHBAR value is not updated by command access.
Section 21 FSI Interface • FSIWDRLH Bit Bit Name 7 to 0 bit 15 to bit 8 R/W Initial Value EC Host Description All 0 R ⎯ These bits store bits [15:8] of the SPI flash memory write data. • FSIWDRLL Bit Bit Name Initial Value 7 to 0 bit 7 to bit 0 All 0 R/W EC Host Description R ⎯ Rev. 2.00 Sep. 28, 2009 Page 702 of 994 REJ09B0452-0200 These bits store bits [7:0] of the SPI flash memory write data.
Section 21 FSI Interface 21.4 Operation 21.4.1 LPC/FW Memory Cycles In LPC/FW memory read and write cycles, data is transferred using LAD3 to LAD0 synchronously with LCLK. The order of data transfer is shown in table 21.4. In a cycle returning synchronization signal from the slave, the slave usually returns B'1010 to notify the host of error occurrence; while the FSI in this LSI always returns B'0000 (Ready) or B'0110 (Long wait).
Section 21 FSI Interface LPC Memory Read Cycles State Driven by Value (3 to 0) Counts Content Content Driven by Value (3 to 0) 14 Synchronization Slave 0000 Turn-around None ZZZZ 15 Data 1 Slave bit 3 to bit 0 Wait* Slave 0110 16 Data 2 Slave bit 7 to bit 4 Synchronization Slave 0000 17 Turn-around (recovery) Slave 1111 Turn-around (recovery) Slave 1111 Turn-around None ZZZZ Turn-around None ZZZZ 18 Note: * LPC Memory Write Cycles The number of wait cycles depends o
Section 21 FSI Interface State Counts Content FW Memory Read Cycles FW Memory Write Cycles Driven by Value (3 to 0) Content Driven by Value (3 to 0) 17 Turn-around (recovery) Slave 1111 Turn-around (recovery) Slave 1111 18 Turn-around None ZZZZ Turn-around None ZZZZ Note: * The number of wait cycles depends on the system clock. The FSI supports byte, word, and longword transfers of FW memory read and write cycles.
Section 21 FSI Interface 21.4.3 Flash Memory Instructions Table 21.6 lists the flash memory instructions (INS). Table 21.
Section 21 FSI Interface 21.4.4 FSI Memory Cycle (Direct Transfer between LPC and SPI) The FSI supports direct transfer between the host and SPI flash memory. If the host address input in LPC/FW memory write cycle matches the host address set in FSIHBARH, FSIHBARL, or FSISR, the FSI memory cycle starts. In LPC/FW memory write cycle, the FSI supports three types of instructions: Byte/Page-Program instructions and AAI-Program instruction.
Section 21 FSI Interface (2) Byte/Page-Program Instruction If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 and the FSIDMYE bit in FSILSTR1 are cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to 1, the SPI flash memory address and write data are stored in FSIAR and FSIWDR, respectively. Then, the SPI flash memory address, the write data, and the Byte/Page-Program instruction which is stored in FSIPPINS in advance are transferred to FSITDR.
Section 21 FSI Interface LCLK LFRAME LAD[3:0] ST CT ADDR DATA TAR SY TAR WAIT φ FSIAR[23:0] H'06-4A-70 H'67-45-23-01 FSIWDR[31:0] FSIPPINS[7:0] H'02 FSICR2 TE bit FSITDR7 to FSITDR0 H'67-45-23-01-70-4A-06-02 FSISTR OBF bit FSISS FSICK (CPOS = CPHS = 0) FSIDO H'02->06->4A->70->01->23->45->67 Figure 21.5 Page-Program Instruction Execution Timing Rev. 2.00 Sep.
Section 21 FSI Interface (3) AAI-Program Instruction If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 is set to 1 and the FSIDMYE bit in FSILSTR1 is cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to 1, the flash memory address and write data are stored in FSIAR and FSIWDR, respectively. Then, the flash memory address, write data, and the AAI-Program instruction which is stored in FSI hardware in advance are transferred to FSITDR.
Section 21 FSI Interface LCLK LFRAME LAD[3:0] CT ADDR DATA TAR WAIT SY TAR φ FSIAR[23:0] H'06-4A-70 FSIWDR[31:0] H'23 FSICR2 TE bit FSITDR7 to FSITDR0 H'23-AF FSISTR OBF bit FSISS FSICK (CPOS = CPHS =0) FSIDO H'AF->23 Figure 21.7 AAI-Program Instruction Execution Timing (Second and Following Bytes) (4) Read Instructions If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is cleared to 0, the SPI flash memory address is stored in FSIAR.
Section 21 FSI Interface First receive data Internal register H'06_4A_70 FSIRDINS[7:0] FSIRDR3 Second receive data H'23 H'67_45_23_01 FSIAR[23:0] H'01 FSIAR[7:0] H'70 FSIAR[15:8] H'4A FSIAR[23:16] H'06 H'03 H'03 FSIDI Third receive data H'45 Fourth receive data H'67 FSIRDR0 FSITDR3 FSITDR0 FSISFR FSIDO Figure 21.
Section 21 FSI Interface (5) Fast-Read Instruction If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is set to 1, the host address is stored in FSIAR. Then, the SPI flash memory address and the instruction which is stored in FSIRDINS in advance are transferred to FSITDR. After SYNC (long wait) has been returned, the RE bit in FSICR2 is set, and Fast-Read instruction execution starts. The read data is then received and stored in FSIRDR.
Section 21 FSI Interface 21.4.5 FSI Memory Cycle (LPC-SPI Command Transfer) The FSI supports instructions other than Byte/Page-Program instructions, AAI-Program instruction, Read instruction, and Fast-Read instruction by using an LPC-SPI command transfer. (1) FSI Command Space Specific host address space can be used as FSI command space according to the CMDHBAR settings. Figure 21.11 shows an example of FSI command space settings.
Section 21 FSI Interface (2) FSI Command Write If an LPC/FW memory write cycle for the FSI command space occurs, the FSI performs the FSIFLASH command write operation. Figure 21.12 shows an example of FSI Command write operation.
Section 21 FSI Interface (3) FSI Command Read Figure 21.13 shows an example of FSI command read. CMDHBAR: H'EFFF H'EFFF_0000∗ H'EFFF_F000 CMD0 CMD1 FSILSTR1 FSIGPR1 FSIGPR2 to D H'EFFF_F00F CMDE CMDF LPC internal flags EC CPU write FSIGPRE FSIGPRF H'EFFF_FFFF Host address Note: * The upper 16 bits of the host address are set to the value in the CMDHBAR register. Figure 21.13 FSI Command Read (Example) As shown in figure 21.
Section 21 FSI Interface (4) FSI Dummy Write Figure 21.14 shows an example of FSI dummy write. FSI Dummy Write FSIHBAR: H'231F FSISR: H'00 (1 MB) CMDHBAR: H'EFFF FSIDMYE B'1 FSIWDR[31:0] H'2325_4A76 H'73 Host address H'0000_0073 FSIAR[23:0] H'06_4A76 Byte-Program FSIDMYE B'0 SPI Flash memory FSIWDR[31:0] H'232E_1BC3 H'D4 Host address H'D4 H'0000_00D4 FSIAR[23:0] H'0F_1BC3 Flash memory address H'0F_1BC3 Figure 21.14 FSI Dummy Write (Example) As shown in figure 21.
Section 21 FSI Interface (5) FSI Command Usage Example 1 (SPI Flash Memory Erasure) The FSI commands enable the execution of several instructions for the SPI flash memory. Figure 21.15 shows an example of executing the SPI flash memory erasure instruction.
Section 21 FSI Interface STEP1 STEP2 STEP3 φ FSIDMYE Written by the CPU FSICMDI Cleared by the CPU CMDBUSY Cleared by the CPU LPC_ADDR FSIAR[23:0] H'EFFF_F000 Cleared by the CPU Cleared by the CPU Cleared by the CPU H'2325_4A76 H'EFFF_F000 H'06_4A76 TE Automatically cleared Written by the CPU Written by the CPU H'4 TBN FSITDR3 to FSITDR1 H'00 (Automatically cleared) Written by the CPU H'76-4A-06 FSIINS Written by the CPU H'52 OBF Cleared by the CPU FSITEI FSISS FSICK H'52->76->4A->
Section 21 FSI Interface 4. Execute the SPI flash memory erasure instruction. ⎯ Set the TE bit in FSICR2 to 1. ⎯ Set the TBN bit in FSIBNR to 4-byte transfer. ⎯ Write the FSI address stored in FSIAR to FSITDR1 to FSITDR3. ⎯ Write the erasure instruction to FSIINS (start the SPI flash memory erasure instruction execution). 5. Complete the interrupt processing. 6. Generate an FSITEI interrupt request. 7. Clear the FSIDMYE and CMDBUSY bits in FSILSTR1 to 0. 8. Complete the interrupt processing. 9.
Section 21 FSI Interface Step 1: 1. Write a status read setting command (Host). 2. Generate an FSICMDI interrupt request. 3. Clear the FSICMDI bit in FSILSTR1 to 0. 4. Check that the CMDBUSY bit in FSILSTR1 is set to 1 and that the FSICMDI bit in FSILSTR1 is cleared to 0 (Host). Step 2: 1. Perform the SPI flash memory status read instruction. ⎯ Set the RE bit in FSICR2 to 1. ⎯ Set the TBN bit in FSIBNR to 1-byte transfer and set the RBN bit in FSIBNR to 1-byte reception.
Section 21 FSI Interface 21.4.6 SPI Flash Memory Write Operation Mode The write operation to the SPI flash memory in the LPC/FW memory write cycles can be classified into the following four operation modes, depending or the state of FLDCT and FLWAIT. Table 21.7 SPI Flash Memory Write Operation in LPC/FW Memory Write Cycles Operation Mode FLDCT FLWAIT Selected Register Operation Mode 1 0 0 FSIWBUSY ← 1 Control the write operation to the SPI flash memory by the EC CPU.
Section 21 FSI Interface 21.5 Reset Conditions The FSI supports the LPC shut-down mode. The range of initialization in each mode is shown in table 21.8. Table 21.
Section 21 FSI Interface Register Name System Reset LPC Reset LPC Shutdown LPC Abort FSI Reset FSICR1 Bits 7 to 0 Initialized Retained Retained Retained Retained FSICR2 Bits 7 and 6 Initialized Retained Retained Retained Initialized Bits 5 to 0 Initialized Retained Retained Retained Retained Bits 7 to 4 Initialized Retained Retained Retained Initialized FSIBNR Bit 3 Initialized Retained Retained Retained Retained Bits 2 to 0 Initialized Retained Retained Retained
Section 21 FSI Interface 21.6 Interrupt Sources The FSI has four interrupt sources for the slave (this LSI): FSITEI, FSIRXI, FSICMDI, and FSIWI. FSITEI is a transmit end interrupt when the slave executes the SPI flash memory write transfer. FSIRXI is a receive end interrupt when the slave executes the SPI flash memory read transfer. FSICMDI is a command receive interrupt in host FSI command write. FSIWI is a write receive interrupt in the case of write from the host to the SPI flash memory.
Section 21 FSI Interface Rev. 2.00 Sep.
Section 22 A/D Converter Section 22 A/D Converter This LSI includes one unit (unit 0) of successive-approximation-type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. Figure 22.1 shows a block diagram for unit 0. 22.
Section 22 A/D Converter Internal data bus AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 + φ – Multiplexer Comparator ADCR ADCSR ADDRH ADDRG ADDRF ADDRE ADDRD ADDRC ADDRB 10-bit D/A ADDRA AVref Successive approximation register AVCC Bus interface Module data bus φ/2 Control circuit φ/4 φ/8 Sample-andhold circuit ADI interrupt signal Conversion start trigger from TPU or 8-bit timer [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: A/D control register A/D c
Section 22 A/D Converter 22.2 Input/Output Pins Table 22.1 summarizes the pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The AVref pin is a reference voltage pin for the A/D converter. The sixteen analog input pins are divided into two channel sets: analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0 and analog input pins 8 to 15 (AN8 to AN15) comprising channel set 1. Table 22.
Section 22 A/D Converter 22.3 Register Descriptions The A/D converter has the following registers. Table 22.
Section 22 A/D Converter 22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers which store a conversion result for each channel are shown in table 22.3. The 10-bit conversion data is stored in bits 15 to 6. The lower six bits are always read as 0. The data bus between the CPU and the A/D converter is sixteen bits wide. The data can be read directly from the CPU.
Section 22 A/D Converter 22.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D converter operation. Bit Bit Name Initial Value R/W 7 ADF 0 Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
Section 22 A/D Converter Bit Bit Name Initial Value R/W Description 3 CH3 0 R/W Channel Select 3 to 0 2 CH2 0 R/W 1 CH1 0 R/W Select analog input channels with the SCANE and SCANS bits in ADCRS. 0 CH0 0 R/W The input channel setting must be made when conversion is halted (ADST = 0).
Section 22 A/D Converter 22.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 6 TRGS0 0 R/W Enable the start of A/D conversion by a trigger signal.
Section 22 A/D Converter 22.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. First, select the clock used in A/D conversion. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set at the same time the operating mode or analog input channel is changed. 22.4.
Section 22 A/D Converter 22.4.2 Scan Mode In scan mode, A/D conversion is performed sequentially on the specified channels (max. four channels or eight channels). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by software, the TPU, or the TMR, A/D conversion starts on the first channel in the selected channel set. 2.
Section 22 A/D Converter 22.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 22.2 shows the A/D conversion timing. Table 22.4 indicates the A/D conversion time. As indicated in figure 22.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL).
Section 22 A/D Converter Table 22.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 CKS1 = 1 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. A/D conversion start delay time tD (4) ⎯ (5) (6) ⎯ (9) (10) ⎯ (17) (18) ⎯ (33) Input sampling time tSPL ⎯ 15 ⎯ ⎯ 30 ⎯ ⎯ 60 ⎯ ⎯ 120 ⎯ A/D conversion time tCONV 44 ⎯ 45 8x ⎯ 8x 16x ⎯ 16x 32x ⎯ 32x Note: Values in the table indicate the number of states. Table 22.
Section 22 A/D Converter 22.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. If the ADF bit in ADCSR has been set to 1 after A/D conversion ends and the ADIE bit is set to 1, an ADI interrupt request is enabled. Table 22.6 A/D Converter Interrupt Source Name Interrupt Source Interrupt Flag ADI A/D conversion end ADF 22.6 A/D Conversion Accuracy Definitions This LSI’s A/D conversion accuracy definitions are given below.
Section 22 A/D Converter Digital output Ideal A/D conversion characteristic H'3FF H'3FE H'3FD H'004 H'003 Quantization error H'002 H'001 H'000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 22.3 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 22.4 A/D Conversion Accuracy Definitions Rev. 2.00 Sep.
Section 22 A/D Converter 22.7 Usage Notes 22.7.1 Module Stop Mode Setting The A/D converter operation can be enabled or disabled using the module stop control register. With the initial setting, the A/D converter is stopped. Register access is enabled by canceling module stop mode. For details, see section 26, Power-Down Modes. 22.7.
Section 22 A/D Converter 22.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not interfere with digital signals on the mounting board, so acting as antennas. 22.7.
Section 22 A/D Converter 22.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage of the analog input pins (AN0 to AN15) and analog reference voltage pin (AVref) due to an abnormal voltage such as an excessive surge should be connected between AVcc and AVss, as shown in figure 22.6. Also, the bypass capacitors connected to AVcc and AVref, and the filter capacitors connected to AN0 to AN15 must be connected to AVss.
Section 22 A/D Converter Table 22.7 Analog Pin Specifications Item Min. Max. Unit Analog input capacitance ⎯ 20 pF Permissible signal-source impedance ⎯ 5 kΩ 10 kΩ AN0 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 22.7 Analog Input Pin Equivalent Circuit 22.7.
Section 22 A/D Converter 22.7.8 Note on Activation of the A/D Converter by an External Trigger When starting of the A/D converter by an external trigger* is in use, any of the following actions (1. to 3.) may lead to a situation where stopping of the A/D converter is not possible. Note: * External trigger: Conversion-start trigger from the peripheral modules (TMU and TPU) 1. Changing the value of the ADST bit in ADCSR from 0 to 1 2.
Section 22 A/D Converter Extaernal trigger shut off? Yes No ADCR.TRGS1 = 0 ADCR.TRGS0 = 0 (to invalidate the external trigger)* ADCSR.ADST = 0 Change the scan mode change the extaernal trigger setting* Note * Overwrite the TRGS1 and TRGS0 bits settings at the same time (in a byte unit). Figure 22.8 Procedure for Changing Modes when Starting of the A/D Converter by an External Trigger has been Selected Rev. 2.00 Sep.
Section 23 RAM Section 23 RAM This LSI has 8 Kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU for both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Rev. 2.00 Sep.
Section 23 RAM Rev. 2.00 Sep.
Section 24 Flash Memory Section 24 Flash Memory The flash memory has the following features. Figure 24.1 is a block diagram of the flash memory. 24.1 Features • Size Product Classification H8S/2117R R4F2117R ROM Size ROM Address 160 kbytes H'000000 to H'027FFF (mode 2) • Two flash-memory MATs according to LSI initiation mode. The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs).
Section 24 Flash Memory • Programming/erasing protection Protection against programming/erasing of the flash memory can be set by hardware protection, software protection, or error protection.
Section 24 Flash Memory RES = 0 Reset state = RE S End of programming/ erasure User program mode User mode Start of programming/ erasure RE S Bo ot 0 = S RE e od tm oo g r b ettin s 0 e Us 0 S= ing RE ett es d mo er Us Programmer mode setting m od e se = Programmer mode 0 tti ng User boot mode Boot mode On-board programming mode Figure 24.2 Mode Transition of Flash Memory Table 24.
Section 24 Flash Memory • The user boot MAT can be programmed or erased only in boot mode and programmer mode. • In boot mode, the user boot MAT are totally erased. Then, the user MAT or user boot MAT can be programmed by means of commands. Note that the contents of the MAT cannot be read until this state. Boot mode can be used for programming only the boot MAT and then programming the user MAT in user boot mode. Another way is to program only the user MAT since user boot mode is not used.
Section 24 Flash Memory 24.4 Block Structure Figure 24.4 shows the 160-kbyte block structure. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames indicates the addresses. The 160-kbyte user MAT is divided into one 64-kbyte block, two 32-kbyte blocks, and eight 4-kbyte blocks. The user MAT can be erased in these block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80.
Section 24 Flash Memory 24.5 Programming/Erasing Interface Programming/erasing of the flash memory is done by downloading an on-chip programming/erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters. The procedure program for user program mode/user boot mode is made by the user. Figure 24.
Section 24 Flash Memory (1) Selection of On-Chip Program to be Downloaded This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by the programming/erasing interface registers. The start address of the on-chip RAM where an on-chip program is downloaded is specified by the flash transfer destination address register (FTDAR).
Section 24 Flash Memory (5) When Programming/Erasing is Executed Consecutively When processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasing can be realized by updating the start address of the programming destination and program data, or the erase block number. Since the downloaded on-chip program is left in the on-chip RAM even after programming/erasing completes, download and initialization are not required when the same processing is executed consecutively.
Section 24 Flash Memory 24.7 Register Descriptions The flash memory has the following registers and parameters. Table 24.
Section 24 Flash Memory There are several operating modes for accessing the flash memory. Respective operating modes, registers, and parameters are assigned to the user MAT. The correspondence between operating modes and registers/parameters for use is shown in table 24.5. Table 24.
Section 24 Flash Memory 24.7.1 Programming/Erasing Interface Registers The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a power-on reset. (1) Flash Code Control/Status Register (FCCS) FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM.
Section 24 Flash Memory Bit Initial Bit Name Value R/W Description 3 to 1 ⎯ R Reserved All 0 These are read-only bits and cannot be modified. 0 SCO 0 (R)/W* Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR.
Section 24 Flash Memory (2) Flash Program Code Select Register (FPCS) FPCS selects the programming program to be downloaded. Bit Initial Bit Name Value R/W 7 to 1 ⎯ R All 0 Description Reserved These are read-only bits and cannot be modified. 0 PPVS 0 R/W Program Pulse Verify Selects the programming program to be downloaded. 0: Programming program is not selected. [Clearing condition] When transfer is completed 1: Programming program is selected.
Section 24 Flash Memory (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasing of the flash memory. Bit Initial Bit Name Value R/W Description 7 K7 0 R/W Key Code 6 K6 0 R/W 5 K5 0 R/W 4 K4 0 R/W 3 K3 0 R/W When H'A5 is written to FKEY, writing to the SCO bit in FCCS is enabled. When a value other than H'A5 is written, the SCO bit cannot be set to 1.
Section 24 Flash Memory (5) Flash MAT Select Register (FMATS) FMATS specifies whether the user MAT or user boot MAT is selected. Bit Initial Bit Name Value 7 MS7 0/1* R/W* 6 MS6 0 R/W* 1 1 R/W Description 2 MAT Select 2 The user MAT is selected when a value other than H'AA is written, and the user boot MAT is selected when H'AA is written. The MAT is switched by writing a value in FMATS. To switch the MAT, make sure to follow section 24.10, Switching between User MAT and User Boot MAT.
Section 24 Flash Memory (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1. Bit Initial Bit Name Value R/W 7 TDER R/W 0 Description Transfer Destination Address Setting Error This bit is set to 1 when an error has occurred in setting the start address specified by bits TDA6 to TDA0.
Section 24 Flash Memory 24.7.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area.
Section 24 Flash Memory (b) Initialization before Programming/Erasing The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has been downloaded to perform these settings.
Section 24 Flash Memory (1) Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in OnChip RAM Specified by FTDAR) DPFR indicates the return value of the download result. The DPFR value is used to determine the download result. Bit Initial Bit Name Value R/W Description 7 to 3 ⎯ ⎯ Unused ⎯ These bits return 0. 2 SS ⎯ R/W Source Select Error Detect Only one type can be specified for the on-chip program which can be downloaded.
Section 24 Flash Memory (2) Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. (a) Initialization before programming/erasing FPFR indicates the return value of the initialization result. Bit Bit Name Initial Value R/W Description 7 to 2 ⎯ ⎯ ⎯ Unused 1 FQ ⎯ R/W These bits return 0.
Section 24 Flash Memory (b) Programming FPFR indicates the return value of the programming result. Bit Bit Name Initial Value R/W Description 7 ⎯ ⎯ ⎯ Unused Returns 0. 6 MD ⎯ R/W Programming Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS.
Section 24 Flash Memory Bit Initial Bit Name Value 2 WD ⎯ R/W Description R/W Write Data Address Detect When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs. 0: Setting of the start address of the storage destination for the program data is normal 1: Setting of the start address of the storage destination for the program data is abnormal 1 WA ⎯ R/W 0 SF ⎯ R/W Rev. 2.00 Sep.
Section 24 Flash Memory (c) Erasure FPFR indicates the return value of the erasure result. Bit Initial Bit Name Value R/W Description 7 ⎯ ⎯ Unused ⎯ Returns 0. 6 MD ⎯ R/W Erasure Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS.
Section 24 Flash Memory Bit Initial Bit Name Value 3 EB ⎯ R/W Description R/W Erase Block Select Error Detect Checks whether the specified erase block number is in the block range of the user MAT, and returns the result. 0: Setting of erase block number is normal 1: Setting of erase block number is abnormal 2, 1 ⎯ ⎯ ⎯ Unused These bits return 0. 0 SF ⎯ R/W Success/Fail Indicates the erasure result.
Section 24 Flash Memory (3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) FPEFEQ sets the operating frequency of the CPU. The operating frequency available in this LSI ranges from 8 MHz to 20 MHz. Bit Initial Bit Name Value 31 to 16 ⎯ ⎯ R/W Description ⎯ Unused These bits should be cleared to 0. 15 to 0 F15 to F0 ⎯ R/W Frequency Set These bits set the operating frequency of the CPU. The setting value must be calculated as follows: 1.
Section 24 Flash Memory (4) Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU) FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs. The error occurrence is indicated by the WA bit in FPFR.
Section 24 Flash Memory (6) Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) FEBS specifies the erase block number. Settable values range from 0 to 10 (H'00000000 to H'0000000A). A value of 0 corresponds to block EB0 and a value of 10 corresponds to block EB10. Do not set a value outside the range from 0 to 10. Bit Initial Bit Name Value 31 to 8 ⎯ R/W Undefined R/W Description Unused These bits should be set to 0.
Section 24 Flash Memory 24.8 On-Board Programming Mode When the mode pins (MD1 and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. On-board programming mode has three operating modes: boot mode, user boot mode, and user program mode. Table 24.7 shows the pin setting for each operating mode.
Section 24 Flash Memory (1) Serial Interface Setting by Host The SCI_1 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to boot mode is made, the boot program embedded in this LSI is initiated.
Section 24 Flash Memory (2) State Transition Diagram The state transition after boot mode is initiated is shown in figure 24.8. (Bit rate adjustment) H'00, ..., H'00 reception Boot mode initiation (reset by boot mode) H'00 transmission (adjustment completed) Bit rate adjustment H'55 re Inquiry command reception Wait for inquiry setting command 2. Inquiry command response 3. 4.
Section 24 Flash Memory 1. After boot mode is initiated, the bit rate of the SCI_1 is adjusted with that of the host. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT and user boot MAT are automatically erased. 4. When the program preparation notice is received, the state of waiting for program data is entered.
Section 24 Flash Memory 24.8.2 User Program Mode Programming/erasing of the user MAT is executed by downloading an on-chip program. The programming/erasing flow is shown in figure 24.10. Since high voltage is applied to the internal flash memory during programming/erasing, a transition to the reset state must not be made during programming/erasing. A transition to the reset state during programming/erasing may damage the flash memory.
Section 24 Flash Memory (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that is made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the onchip program and procedure program do not overlap. Figure 24.11 shows the area of the on-chip program to be downloaded.
Section 24 Flash Memory (2) Programming Procedure in User Program Mode Start programming procedure program 1 Select on-chip program to be downloaded and specify download destination by FTDAR 1. Disable interrupts and bus master operation other than CPU 8. Set FKEY to H'5A 9. Set FKEY to H'A5 2. Set SCO to 1 after initializing VBR and execute download 2. Set parameters to ER1 and ER0 (FMPAR and FMPDR) 10. Clear FKEY to 0 3. Programming JSR FTDAR setting + 16 11. 4.
Section 24 Flash Memory The procedure program must be executed in an area other than the flash memory to be programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the onchip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data.
Section 24 Flash Memory ⎯ To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed. ⎯ Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1. 3. FKEY is cleared to H'00 for protection. 4. The download result must be confirmed by the value of the DPFR parameter. Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR).
Section 24 Flash Memory 7. The return value in the initialization program, the FPFR parameter is determined. 8. All interrupts and the use of a bus master other than the CPU are disabled during programming/erasing. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during programming/erasing, causing a voltage exceeding the specifications to be applied, the flash memory may be damaged.
Section 24 Flash Memory 12. The return value in the programming program, the FPFR parameter is determined. 13. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, update the FMPAR and FMPDR parameters in 128-byte units, and repeat steps 11 to 14. Increment the programming destination address by 128 bytes and update the programming data pointer correctly.
Section 24 Flash Memory (3) Erasing Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and erasing are shown in figure 24.13. Start erasing procedure program 1 Set FKEY to H'A5 Set FKEY to H'5A Set SCO to 1 and execute download Set FEBS parameter 2. Erasing JSR FTDAR setting + 16 3. Clear FKEY to 0 DPFR = 0? Yes Yes Download error processing No Initialization JSR FTDAR setting + 32 4.
Section 24 Flash Memory One erasure processing erases one block. For details on block divisions, refer to figure 24.4. To erase two or more blocks, update the erase block number and repeat the erasing processing for each block. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time.
Section 24 Flash Memory 24.8.3 User Boot Mode This LSI has user boot mode that is initiated with different mode pin settings than those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode.
Section 24 Flash Memory Start erasing procedure program 1 Select on-chip program to be downloaded and specify download destination by FTDAR Set FMATS to value other than H'AA to select user MAT MAT switchover Set FKEY to H'A5 Yes No Download error processing Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0? Set parameters to ER0 and ER1 (FMPAR and FMPDR) Programming Clear FKEY to 0 User-MAT selection state Download Set SCO to 1 and execute download DPFR = 0? Initiali
Section 24 Flash Memory MAT switching is enabled by writing a specific value to FMATS. Note, however, that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined. Perform MAT switching in accordance with the description in section 24.10, Switching between User MAT and User Boot MAT.
Section 24 Flash Memory Start erasing procedure program 1 Select on-chip program to be downloaded and specify download destination by FTDAR Set FMATS to value other than H'AA to select user MAT MAT switchover Set FKEY to H'A5 Yes No Download error processing Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0? Set FEBS parameter Programming JSR FTDAR setting + 16 Erasing Clear FKEY to 0 User-MAT selection state Download Set SCO to 1 and execute download DPFR = 0? Initia
Section 24 Flash Memory Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data. 24.8.4 Storable Areas for On-Chip Program and Program Data In the descriptions in this manual, the on-chip programs and program data storage areas are assumed to be in the on-chip RAM.
Section 24 Flash Memory In consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory MATs, as shown in tables 24.9 to 24.13. Table 24.9 Executable Memory MAT Operating Mode Processing Contents User Program Mode User boot Mode* Programming See table 24.10. See table 24.12 Erasing See table 24.11. See table 24.
Section 24 Flash Memory Table 24.
Section 24 Flash Memory Table 24.
Section 24 Flash Memory Table 24.
Section 24 Flash Memory 24.9 Protection There are three types of protection against the flash memory programming/erasing: hardware protection, software protection, and error protection. 24.9.1 Hardware Protection Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection. In this state, download of an on-chip program and initialization are possible.
Section 24 Flash Memory 24.9.2 Software Protection The software protection protects the flash memory against programming/erasing by disabling download of the programming/erasing program and using the key code. Table 24.15 Software Protection Function to be Protected Item Description Download Programming/ Erasing Protection The programming/erasing protection state is O by SCO bit entered when the SCO bit in FCCS is cleared to 0 to disable download of the programming/erasing programs.
Section 24 Flash Memory Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100μs has passed. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damaging the flash memory by extending the reset input period so that the charge is released. The state-transition diagram in figure 24.
Section 24 Flash Memory 24.10 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because both of these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. 2.
Section 24 Flash Memory 24.11 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 24.16 can be used to write programs to the on-chip ROM without any limitation. Table 24.
Section 24 Flash Memory 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. These boot program states are shown in figure 24.18.
Section 24 Flash Memory (1) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 24.19.
Section 24 Flash Memory 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. 5. Memory read response This response consists of four bytes of data.
Section 24 Flash Memory (3) Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 24.17 lists the inquiry and selection commands. Table 24.
Section 24 Flash Memory The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40).
Section 24 Flash Memory (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made.
Section 24 Flash Memory (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands.
Section 24 Flash Memory (e) Division Ratio Inquiry The boot program will return the supported division ratios in response to the inquiry.
Section 24 Flash Memory (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values.
Section 24 Flash Memory (g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses.
Section 24 Flash Memory (h) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses.
Section 24 Flash Memory • Block last Address (four bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are areas. • SUM (one byte): Checksum (j) Programming Unit Inquiry The boot program will return the programming unit used to program data.
Section 24 Flash Memory • Number of division ratios (one byte): The number of division ratios to which the device can be set. There are usually two division ratios, which are the main and peripheral module operating frequencies. • Division ratio 1 (one byte): The value of division ratios for the main operating frequency Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE.
Section 24 Flash Memory (4) Receive Data Check The methods for checking of receive data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2.
Section 24 Flash Memory The sequence of new bit-rate selection is shown in figure 24.21. Boot program Host Setting a new bit rate H'06 (ACK) Waiting for one-bit period at the specified bit rate Setting a new bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Figure 24.
Section 24 Flash Memory (6) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples.
Section 24 Flash Memory (8) Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 24.18 lists the programming/erasing commands. Table 24.
Section 24 Flash Memory 1. Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command. After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command.
Section 24 Flash Memory 2. Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing.
Section 24 Flash Memory 3. Programming/Erasing State Information (a) User Boot MAT Programming Selection The boot program will transfer a program for user boot MAT programming selection. The data is programmed to the user boot MATs by the transferred program for programming.
Section 24 Flash Memory (c) 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user MATs in response to 128-byte programming. Command H'50 Address Data … … SUM • Command, H'50, (one byte): 128-byte programming • Programming Address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e.
Section 24 Flash Memory Command H'50 Address SUM • Command, H'50, (one byte): 128-byte programming • Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. • SUM (one byte): Checksum Response H'06 • Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK.
Section 24 Flash Memory (e) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM • Command, H'58, (one byte): Erasure • Size (one byte): The number of bytes that represents the erase block number This is fixed to 1. • Block number (one byte): Number of the block to be erased • SUM (one byte): Checksum Response H'06 • Response, H'06, (one byte): Response to Erasure After erasure has been completed, the boot program will return ACK.
Section 24 Flash Memory (f) Memory Read The boot program will return the data in the specified address. Command H'52 Size Area Read address Read size SUM • Command: H'52 (1 byte): Memory read • Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) • Area (1 byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect.
Section 24 Flash Memory (g) User Boot MAT Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user boot MAT. Command H'4A • Command, H'4A, (one byte): Sum check for user boot MAT Response H'5A Size Checksum of MAT SUM • Response, H'5A, (one byte): Response to the sum check of the user boot MAT • Size (one byte): The number of bytes that represents the checksum This is fixed to 4.
Section 24 Flash Memory (i) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C • Command, H'4C, (one byte): Blank check for user boot MATs Response H'06 • Response, H'06, (one byte): Response to the blank check for user boot MATs If the contents of all user boot MATs are blank (H'FF), the boot program will return ACK.
Section 24 Flash Memory (k) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F • Command, H'4F, (one byte): Response H'5F Size Inquiry regarding boot program's state Status ERROR SUM • Response, H'5F, (one byte): Response to boot program state inquiry • Size (one byte): The number of bytes. This is fixed to 2.
Section 24 Flash Memory Table 24.
Section 24 Flash Memory 24.13 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3.
Section 24 Flash Memory 12. If data other than H'FF is to be written to the key code area in programmer mode, a verification error will occur unless a software countermeasure is taken for the PROM programmer and version of program. 13. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 kbytes or less.
Section 25 Clock Pulse Generator Section 25 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock, bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, duty correction circuit, system clock select circuit, subclock input circuit, and subclock waveform forming circuit. Figure 25.1 shows a block diagram of the clock pulse generator.
Section 25 Clock Pulse Generator 25.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 25.1.1 Connecting Crystal Resonator Figure 25.2 shows a typical method for connecting a crystal resonator. An appropriate damping resistance Rd, given in table 25.1 should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 25.3 shows an equivalent circuit of a crystal resonator.
Section 25 Clock Pulse Generator Table 25.2 Crystal Resonator Parameters Frequency (MHz) 8 10 12 16 20 RS (max) (Ω) 80 70 60 50 40 C0 (max) (pF) 7 7 7 7 7 25.1.2 External Clock Input Method Figure 25.4 shows a typical method of inputting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode or watch mode.
Section 25 Clock Pulse Generator Table 25.3 External Clock Input Conditions VCC = 3.0 to 3.6 V Item Symbol Min. Max. Unit Test Conditions External clock input pulse width low level tEXL 20 ⎯ ns External clock input pulse width high level tEXH 20 ⎯ ns External clock rising time tEXr ⎯ 5 ns External clock falling time tEXf ⎯ 5 ns Clock pulse width low level tCL 0.4 0.6 tcyc Clock pulse width high level tCH 0.4 0.6 tcyc tEXH Figure 25.5 Figure 28.4 tEXL VCC × 0.
Section 25 Clock Pulse Generator Table 25.4 External Clock Output Stabilization Delay Time Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V Item Symbol External clock output stabilization delay tDEXT* time Note: * Min. Max. Unit Remarks 500 ⎯ μs Figure 25.6 tDEXT includes a RES pulse width (tRESW). VCC 3.0 V EXTAL φ (Internal and external) RES tDEXT* Note: * The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW). Figure 25.
Section 25 Clock Pulse Generator 25.2 Duty Correction Circuit The duty correction circuit generates the system clock (φ) by correcting the duty of the clock output from the oscillator. 25.3 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL or ExEXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL or ExEXCL pin. Figure 25.7 shows the relationship of subclock input from the EXCL pin and the ExEXCL pin.
Section 25 Clock Pulse Generator tEXCLH tEXCLL VCC × 0.5 EXCL tEXCLr tEXCLf Figure 25.8 Subclock Input Timing 25.4 Subclock Waveform Forming Circuit To remove noise from the subclock input at the EXCL (ExEXCL) pin, the subclock waveform forming circuit samples the subclock using a divided φ clock. The sampling frequency is set by the NESEL bit in LPWRCR. The subclock is not sampled in watch mode. 25.
Section 25 Clock Pulse Generator 25.6 Usage Notes 25.6.1 Notes on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. Consult with the resonator manufacturer about the resonator circuit ratings that vary depending on the stray capacitances of the resonator and installation circuit.
Section 26 Power-Down Modes Section 26 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has four power-down operating modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules. • Medium-speed mode System clock frequency for the CPU operation can be selected as φ/2, φ/4, φ/8, φ/16 or φ/32.
Section 26 Power-Down Modes 26.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in highspeed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode or watch mode Note that the SSBY bit is not changed even if a mode transition is made by an interrupt.
Section 26 Power-Down Modes Bit Bit Name Initial Value R/W Description 2 SCK2 0 R/W System Clock Select 2 to 0 1 SCK1 0 R/W 0 SCK0 0 R/W These bits select a clock for the bus master in highspeed mode or medium-speed mode. When making a transition to watch mode, these bits must be cleared to B'000.
Section 26 Power-Down Modes 26.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Bit Bit Name Initial Value R/W Description 7 DTON 0 R/W Direct Transfer On Flag The initial value should not be changed. 6 LSON 0 R/W Low-Speed On Flag The initial value should not be changed.
Section 26 Power-Down Modes 26.1.3 Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, MSTPCRB) MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. • MSTPCRH Bit Bit Name Initial Value R/W Corresponding Module 7 MSTP15 0 R/W Reserved 6 MSTP14 0 R/W The initial value should not be changed. Reserved The initial value should not be changed.
Section 26 Power-Down Modes • MSTPCRA Bit Bit Name Initial Value R/W Corresponding Module 7 MSTPA7 Reserved 1 R/W The initial value should not be changed.
Section 26 Power-Down Modes The PWMX sets operation or stop by a combination of bits as follows: MSTPCRH: MSTP11 MSTPCRA: MSTPA1 Function 0 0 14-bit PWM timer (PWMX) operates. 0 1 14-bit PWM timer (PWMX) stops. 1 0 14-bit PWM timer (PWMX) stops. 1 1 14-bit PWM timer (PWMX) stops. Note: The MSTP11 bit in MSTPCRH is a module stop bit of the PWMX. Rev. 2.00 Sep.
Section 26 Power-Down Modes 26.2 Mode Transitions and LSI States Figure 26.1 shows the possible mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The RES input causes a mode transition from any state to the reset state. Table 26.3 shows the LSI internal states in each operating mode.
Section 26 Power-Down Modes Table 26.
Section 26 Power-Down Modes 26.3 Medium-Speed Mode The operating mode changes to medium-speed mode as soon as the current bus cycle ends by the settings of the SCK2 to SCK0 bits in SBYCR. The operating clock can be selected from φ/2, φ/4, φ/8, φ/16, or φ/32. On-chip peripheral functions other than the bus masters and the PS2 operate on the system clock (φ). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock.
Section 26 Power-Down Modes 26.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the on-chip peripheral modules do not. The contents of the CPU’s internal registers are retained. Sleep mode is cleared by any interrupt or the RES pin input. When an interrupt occurs, sleep mode is cleared and interrupt exception handling starts.
Section 26 Power-Down Modes When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. Figure 26.
Section 26 Power-Down Modes 26.6 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and on-chip peripheral modules other than CIR and WDT_1 are also stopped.
Section 26 Power-Down Modes 26.7 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cleared and module operation resumes at the end of the bus cycle.
Section 27 List of Registers Section 27 List of Registers The list of registers gives information on the on-chip register addresses, how the register bits are configured, the register states in each operating mode, the register selection condition, and the register address of each module. The information is given as shown below. 1. • • • • • Register addresses (address order) Registers are listed from the lower allocation addresses. For the addresses of 16 bits, the MSB is described.
Section 27 List of Registers 27.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits. The number of access states indicates the number of states based on the specified reference clock.
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Port 5 data direction register P5DDR 8 H'F920 (PORTS = 1) PORT 8 2 Port 6 data direction register P6DDR 8 H'F921 (PORTS = 1) PORT 8 2 Port 5 data register P5DR 8 H'F922 (PORTS = 1) PORT 8 2 Port 6 data register P6DR 8 H'F923 (PORTS = 1) PORT 8 2 Port 5 input data register P5PIN 8 H'F924 (Read) (PORTS = 1) PORT 8 2 Port 6 input data register P6PIN 8 H'F92
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Port B data direction register PBDDR 8 H'F951 (PORTS = 1) PORT 8 2 Port A output data register PAODR 8 H'F952 (PORTS = 1) PORT 8 2 Port B output data register PBODR 8 H'F953 (PORTS = 1) PORT 8 2 Port A input data register PAPIN 8 H'F954 (Read) (PORTS = 1) PORT 8 2 Port B input data register PBPIN 8 H'F955 (Read) (PORTS = 1) PORT 8 2 Port B pull-up MOS contr
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Port F data direction register PFDDR 8 H'F971 (PORTS = 1) PORT 8 2 Port F output data register PFODR 8 H'F973 (PORTS = 1) PORT 8 2 Port E input data register PEPIN 8 H'F974 (Read) (PORTS = 1) PORT 8 2 Port F input data register PFPIN 8 H'F975 (Read) (PORTS = 1) PORT 8 2 Port F pull-up MOS control register PFPCR 8 H'F977 (PORTS = 1) PORT 8 2 Port F Nch-OD co
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Port I data direction register PIDDR 8 H'F990 PORT 8 2 Port J data direction register PJDDR 8 H'F991 PORT 8 2 Port I output data register PIODR 8 H'F992 PORT 8 2 Port J output data register PJODR 8 H'F993 PORT 8 2 Port I input data register PIPIN 8 H'F994 (Read) PORT 8 2 Port J input data register PJPIN 8 H'F995 (Read) PORT 8 2 Port J pull-up MOS con
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States TDP timer counter_0 TDPCNT_0 16 H'FB40 TDP_0 16 2 TDP pulse width upper limit register_0 TDPWDMX_0 16 H'FB42 TDP_0 16 2 TDP pulse width lower limit register_0 TDPWDMN_0 16 H'FB44 TDP_0 16 2 TDP cycle upper limit register_0 TDPPDMX_0 16 H'FB46 TDP_0 16 2 TDP input capture register_0 TDPICR_0 16 H'FB48 TDP_0 16 2 TDP input capture buffer register_0 TDPICRF_0
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States TDP input capture register_2 TDPICR_2 16 H'FB88 TDP_2 16 2 TDP input capture buffer register_2 TDPICRF_2 16 H'FB8A TDP_2 16 2 TDP status register_2 TDPCSR_2 8 H'FB8C TDP_2 8 2 TDP control register 1_2 TDPCR1_2 8 H'FB8D TDP_2 8 2 TDP interrupt enable register_2 TDPIER_2 8 H'FB8E TDP_2 8 2 TDP control register 2_2 TDPCR2_2 8 H'FB8F TDP_2 8 2 TDP cycle
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States TCM input capture register_3 TCMICR_3 16 H'FBF4 TCM_3 16 2 TCM input capture buffer register_3 TCMICRF_3 16 H'FBF6 TCM_3 16 2 TCM status register_3 TCMCSR_3 8 H'FBF8 TCM_3 8 2 TCM control register_3 TCMCR_3 8 H'FBF9 TCM_3 8 2 TCM interrupt enable register_3 TCMIER_3 8 H'FBFA TCM_3 8 2 TCM cycle lower limit register_3 TCMMINCM_3 16 H'FBFC TCM_3 16 2 A/
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Modem status register FMSR 8 H'FC26 SCIF 8 2 Scratch pad register FSCR 8 H'FC27 SCIF 8 2 SCIF control register SCIFCR 8 H'FC28 SCIF 8 2 FSI access host base address register H FSIHBARH 8 H'FC50 FSI 8 2 FSI access host base address register L FSIHBARL 8 H'FC51 FSI 8 2 FSI flash memory size register FSISR 8 H'FC52 FSI 8 2 FSI command host base address
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States FSI write data register HH FSIWDRHH 8 H'FC6A FSI 8 2 FSI write data register HL FSIWDRHL 8 H'FC6B FSI 8 2 FSI write data register LH FSIWDRLH 8 H'FC6C FSI 8 2 FSI write data register LL FSIWDRLL 8 H'FC6D FSI 8 2 FSILPC command status register 2 FSILSTR2 8 H'FC6E FSI 8 2 FSI control register 1 FSICR1 8 H'FC90 FSI 8 2 FSI control register 2 FSICR2 8
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States PWM prescaler register 5_A PWMPRE5_A 8 H'FD0B PWMU_A 8 2 PWM control register A_A PWMCONA_A 8 H'FD0C PWMU_A 8 2 PWM control register B_A PWMCONB_A 8 H'FD0D PWMU_A 8 2 PWM control register C_A PWMCONC_A 8 H'FD0E PWMU_A 8 2 PWM control register D_A PWMCOND_A 8 H'FD0F PWMU_A 8 2 PWM duty setting register 0_B PWMREG0_B 8 H'FD10 PWMU_B 8 2 PWM prescaler register 0_B
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States SCIF address register H SCIFADRH 8 H'FDC4 LPC 8 2 SCIF address register L SCIFADRL 8 H'FDC5 LPC 8 2 LPC channel 4 address register H LADR4H 8 H'FDD4 LPC 8 2 LPC channel 4 address register L LADR4L 8 H'FDD5 LPC 8 2 Input data register 4 IDR4 8 H'FDD6 LPC 8 2 Output data register 4 ODR4 8 H'FDD7 LPC 8 2 Status register 4 STR4 8 H'FDD8 LPC 8 2 Ho
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Port control register 1 PTCNT1 8 H'FE11 PORT 8 2 Port control register 2 PTCNT2 8 H'FE12 PORT 8 2 Port 9 pull-up MOS control register P9PCR 8 H'FE14 (PORTS = 0) PORT 8 2 Port G Nch-OD control register PGNOCR 8 H'FE16 (PORTS = 0) PORT 8 2 Port F Nch-OD control register PFNOCR 8 H'FE19 (PORTS = 0) PORT 8 2 Port C Nch-OD control register PCNOCR 8 H'FE1C (PO
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States LPC channel 3 address register L LADR3L 8 H'FE35 LPC 8 2 SERIRQ control register 0 SIRQCR0 8 H'FE36 LPC 8 2 SERIRQ control register 1 SIRQCR1 8 H'FE37 LPC 8 2 Input data register 1 IDR1 8 H'FE38 LPC 8 2 Output data register 1 ODR1 8 H'FE39 LPC 8 2 Status register 1 STR1 8 H'FE3A LPC 8 2 Input data register 2 IDR2 8 H'FE3C LPC 8 2 SERIRQ contro
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Port C input data register PCPIN 8 H'FE4E (Read) (PORTS = 0) PORT 8 2 Port C data direction register PCDDR 8 H'FE4E (Write) (PORTS = 0) PORT 8 2 Port D input data register PDPIN 8 H'FE4F (Read) (PORTS = 0) PORT 8 2 Port D data direction register PDDDR 8 H'FE4F (Write) (PORTS = 0) PORT 8 2 Timer control register_0 TCR_0 8 H'FE50 TPU_0 8 2 Timer mode register
Section 27 List of Registers Register Name Abbreviation Number of bits Address Keyboard matrix interrupt register A KMIMRA 8 Wake-up sense control register WUESCR Wake-up input interrupt status register Data Width Access States H'FE83 INT (RELOCATE = 1) 8 2 8 H'FE84 INT 8 2 WUESR 8 H'FE85 INT 8 2 Wake-up enable register WER 8 H'FE86 INT 8 2 Interrupt control register D ICRD 8 H'FE87 INT 8 2 2 Module I C bus control register_2 ICCR_2 8 H'FE88 IIC_2 8 2 I2C bus
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Flash transfer destination address register FTDAR 8 H'FEAE ROM 8 2 Timer start register TSTR 8 H'FEB0 TPU common 8 2 Timer synchro register TSYR 8 H'FEB1 TPU common 8 2 Keyboard control register 1_0 KBCR1_0 8 H'FEC0 PS2_0 8 2 Keyboard data buffer transmit data register_0 KBTR_0 8 H'FEC1 PS2_0 8 2 Keyboard control register 1_1 KBCR1_1 8 H'FEC2 PS2_1 8
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Keyboard control register 1_3 KBCR1_3 8 H'FED2 PS2_3 8 2 Keyboard data buffer transmit data register_3 KBTR_3 8 H'FED3 PS2_3 8 2 I2C bus control extended register_0 ICXR_0 8 H'FED4 IIC_0 8 2 I C bus control extended register_1 ICXR_1 8 H'FED5 IIC_1 8 2 Keyboard control register H_0 KBCRH_0 8 H'FED8 PS2_0 8 2 Keyboard control register L_0 KBCRL_0 8 H'FED9
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Transmit data register_2 TDR_2 8 H'FFA3 SCI_2 8 2 Serial status register_2 SSR_2 8 H'FFA4 SCI_2 8 2 Receive data register_2 RDR_2 8 H'FFA5 SCI_2 8 2 Smart card mode register_2 SCMR_2 8 H'FFA6 SCI_2 8 2 PWMX(D/A) counter H DACNTH 8 H'FFA6 PWMX (RELOCATE = 0) 8 2 PWMX(D/A) data register BH DADRBH 8 H'FFA6 PWMX (RELOCATE = 0) 8 2 PWMX(D/A) counter L DACN
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Port 3 data direction register P3DDR 8 H'FFB4 (PORTS = 0) PORT 8 2 Port 4 data direction register P4DDR 8 H'FFB5 (PORTS = 0) PORT 8 2 Port 3 data register P3DR 8 H'FFB6 (PORTS = 0) PORT 8 2 Port 4 data register P4DR 8 H'FFB7 (PORTS = 0) PORT 8 2 Port 5 data direction register P5DDR 8 H'FFB8 (PORTS = 0) PORT 8 2 Port 6 data direction register P6DDR 8 H'FF
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Timer control register_0 TCR_0 8 H'FFC8 TMR_0 8 2 Timer control register_1 TCR_1 8 H'FFC9 TMR_1 8 2 Timer control/status register_0 TCSR_0 8 H'FFCA TMR_0 8 2 Timer control/status register_1 TCSR_1 8 H'FFCB TMR_1 8 2 Time constant register A_0 TCORA_0 8 H'FFCC TMR_0 16 2 Time constant register A_1 TCORA_1 8 H'FFCD TMR_1 16 2 Time constant register B_0
Section 27 List of Registers Register Name Abbreviation Number of bits Address Module Data Width Access States Input capture register R TICRR 8 H'FFF2 TMR_X 8 2 Time constant register A_Y TCORA_Y 8 H'FFF2 TMR_Y (RELOCATE = 0) 8 2 Input capture register F TICRF 8 H'FFF3 TMR_X 8 2 Time constant register B_Y TCORB_Y 8 H'FFF3 TMR_Y (RELOCATE = 0) 8 2 Keyboard matrix interrupt register A KMIMRA 8 H'FFF3 INT (RELOCATE = 0) 8 2 Timer counter _X TCNT_X 8 H'FFF4 TMR_X 8 2
Section 27 List of Registers 27.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines.
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TDPCNT_0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 TDP_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 14 bit 13 bit 12
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 TDPCSR_1 OVF TDPCR1_1 Bit 3 Bit 2 Bit 1 Bit 0 Module TWDMXOVF TWDMNUDF TPDMXOVF ICPF CMF CKSEG TPDMNUDF TDP_1 CST POCTL TDPMDS CKS2 CKS1 CKS0 TDPIER_1 OVIE TWDMXIE TWDMNIE TPDMXIE ICPIE CMIE TDPIPE TPDMNIE TDPCR2_1 PMMS MCICTL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TDPWDMN_1 bit 15 TDPCNT_2 TDPPDMX_2 TDPPDMN_2 Bit 5 CPSPE Bit 4 IEDG bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCMCSR_0 OVF MAXOVF CMF CKSEG ICPF MINUDF MCICTL ⎯ TCM_0 TCMCR_0 CST POCTL CPSPE IEDG TCMMDS CKS2 CKS1 CKS0 TCMIER_0 OVIE MAXOVIE CMIE TCMIPE ICPIE MINUDIE CMMS ⎯ bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 TCMMINCM_0 bit 15 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCMCNT_3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 TCM_3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TCMMLCM_3 TCMICR_3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module FRBR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCIF FTHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FDLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FIER ⎯ ⎯ ⎯ ⎯ EDSSI ELSI ETBEI ERBFI FDLH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FIIR FIFOE1 FIFOE0 ⎯ ⎯ INTID2 INTID1 INTID0 INTPEND FFCR RCVRTRIG1 RCVRTRIG0 ⎯ ⎯ DMA
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module FSIGPRC bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FSI FSIGPRD bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FSIGPRE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FSIGPRF bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SLCR FSILE FSICMDIE FSIWIE FSIWDRLL FSICR1 ⎯ ⎯ ⎯ FSIARH bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 FSIARM bit15 bit14 bit13 bit12 bit11
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PWMREG0_A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PWMU_A PWMPRE0_A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PWMREG1_A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PWMPRE1_A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PWMREG2_A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PWMPRE2_A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_1 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_1 TMDR_1 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_1 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA TSR_1 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA TCNT_1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bi
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PGNCMC PG7NCMC PG6NCMC PG5NCMC PG4NCMC PG3NCMC PG2NCMC PG1NCMC PG0NCMC PORT PGNCCS ⎯ ⎯ ⎯ ⎯ ⎯ PGNCCK2 PGNCCK1 PGNCCK0 PHPIN ⎯ ⎯ PH5PIN PH4PIN PH3PIN PH2PIN PH1PIN PH0PIN PHDDR ⎯ ⎯ PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR PHODR ⎯ ⎯ PH5ODR PH4ODR PH3ODR PH2ODR PH1ODR PH0ODR PHNOCR ⎯ ⎯ PH5NOCR PH4NOCR PH3NOCR PH2NOCR PH1NOCR PH0NOCR PTCNT0 ⎯ ⎯ ⎯
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ODR3 LPC bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 IBF3B OBF3B MWMF SWMF C/D3 DBU32 IBF3A OBF3A 3 STR3* DBU37 DBU36 DBU35 DBU34 C/D3 DBU32 IBF3 OBF3 HICR5 OBEIE OBEI ⎯ ⎯ SCIFE ⎯ ⎯ ⎯ LADR3H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 LADR3L bit 7 bit 6 bit 5 bit 4 bit 3 ⎯ bit 1 TWRE SIRQCR0 Q/C UPSEL IEDIR SMIE3B SM
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PDPIN PD7PIN PD6PIN PD5PIN PD4PIN PD3PIN PD2PIN PD1PIN PD0PIN PORT PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_0 ⎯ ⎯ BFB BFA MD3 MD2 MD1 MD0 TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_0 TTGE ⎯ ⎯ TCIEV
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module KMIMR KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 INT KMPCR KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR PORT KMIMRA KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 INT WUESCR WUE15SC WUE14SC WUE13SC WUE12SC WUE11SC WUE10SC WUE9SC WUE8SC WUESR WUE15F WUE14F WUE13F WUE12F WUE11F WUE10F WUE9F WUE8F WER WUEE ⎯ ⎯ ⎯
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TSTR ⎯ ⎯ ⎯ ⎯ ⎯ CST2 CST1 CST0 TPU TSYR ⎯ ⎯ ⎯ ⎯ ⎯ SYNC2 SYNC1 SYNC0 KBCR1_0 KBTS PS KCIE KTIE ⎯ KCIF KBTE KTER KBTR_0 KBT7 KBT6 KBT5 KBT4 KBT3 KBT2 KBT1 KBT0 common PS2 KBCR1_1 KBTS PS KCIE KTIE ⎯ KCIF KBTE KTER KBTR_1 KBT7 KBT6 KBT5 KBT4 KBT3 KBT2 KBT1 KBT0 KBCR1_2 KBTS PS KCIE KTIE ⎯ KCIF KBTE KTER KBTR_2 KBT7 KBT6 KBT5 KBT
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module KBCRH_2 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS PS2_2 KBCRL_2 KBE KCLKO KDO ⎯ RXCR3 RXCR2 RXCR1 RXCR0 KBBR_2 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 KBCR2_2 ⎯ ⎯ ⎯ ⎯ TXCR3 TXCR2 TXCR1 TXCR0 ICRES_0 ⎯ ⎯ ⎯ ⎯ CLR3 CLR2 CLR1 CLR0 IIC_0 ICRA ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0 INT ICRB ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICR
Section 27 List of Registers Register Abbreviation 1 SSR_1* RDR_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TDRE RDRF ORER FER PER TEND MPB MPBT SCI_1 (TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ⎯ ⎯ ⎯ ⎯ SDIR SINV ⎯ SMIF C/A CHR PE O/E STOP MP CKS1 CKS0 (GM) (BLK) (PE) (O/E) (BCP1) (BCP0) (CKS1) (CKS0) BRR_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCR_2 TIE RI
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR PORT PBPIN PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN P8DDR ⎯ P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR P7PIN P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR P8DR ⎯ P86DR P85DR P84DR P83DR P8
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module KBCRH_3 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS PS2_3 KBCRL_3 KBE KCLKO KDO ⎯ RXCR3 RXCR2 RXCR1 RXCR0 KBBR_3 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 KBCR2_3 ⎯ ⎯ ⎯ ⎯ TXCR3 TXCR2 TXCR1 TXCR0 TCSR_1 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 TCNT_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TCR_X CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS
Section 27 List of Registers 27.
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module TDPCNT_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDP_0 TDPPDMX_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPPDMN_0 Register Abbreviation Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPWDMX_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPICR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPICRF_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPCSR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPCR1_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPIER_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPCR2_0 Initialized ⎯
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module TDPCR1_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDP_2 TDPIER_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPCR2_2 Register Abbreviation Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TDPWDMN_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMCNT_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMMLCM_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMICR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMICRF_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMCSR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMCR_0 Initialized ⎯ ⎯
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCM_3 TCMMLCM_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMICR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMICRF_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMCSR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMCR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMIER_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCMMINCM_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ADDRA Initialized ⎯ Initialized ⎯ Initialized Initialized ADDRB Initialized ⎯ Initializ
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module FSIHBARH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSI FSIHBARL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSISR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ CMDHRARH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ CMDHRARL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSICMDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSILSTR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSILSTR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSIGPR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSIGPR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSIGPR3 Initialized
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module FSIWDRLH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSI FSIWDRLL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSICR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSICR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSIBNR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSINS Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSIRDINS Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSIPPINS Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSISTR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSITDR0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FSITDR1 Initialized ⎯ ⎯
Section 27 List of Registers HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module PWMCONA_A Initialized ⎯ Initialized ⎯ Initialized Initialized PWMU_A PWMCONB_A Initialized ⎯ Initialized ⎯ Initialized Initialized PWMCONC_A Initialized ⎯ Initialized ⎯ Initialized Initialized PWMCOND_A Initialized ⎯ Initialized ⎯ Initialized Initialized PWMREG0_B Initialized ⎯ Initialized ⎯ Initialized Initialized PWMPRE0_B Initialized ⎯ Initialized ⎯ Initialized Init
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module LADR1H Initialized ⎯ ⎯ ⎯ ⎯ ⎯ LPC LADR1L Initialized ⎯ ⎯ ⎯ ⎯ ⎯ LADR2H Initialized ⎯ ⎯ ⎯ ⎯ ⎯ LADR2L Initialized ⎯ ⎯ ⎯ ⎯ ⎯ SCIFADRH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ SCIFADRL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ LADR4H Initialized ⎯ ⎯ ⎯ ⎯ ⎯ LADR4L Initialized ⎯ ⎯ ⎯ ⎯ ⎯ IDR4 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ODR4 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ STR4 Initialized ⎯ ⎯ ⎯ ⎯ ⎯
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module P9PCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ PORT PGNOCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ PFNOCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ PCNOCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ PDNOCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TWR0MW Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TWR0SW Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TWR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TWR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TWR3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TWR4 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TWR5
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module IDR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ LPC ODR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ STR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ SIRQCR4 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ IDR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ODR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ STR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ HISEL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ HICR0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ HICR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ HICR2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ HICR3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module TGRA_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TPU_0 TGRB_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TGRC_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TGRD_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TMDR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TIOR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TIER_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TSR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCNT_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TGRA_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module DACR Initialized ⎯ Initialized ⎯ Initialized Initialized PWMX DADRA Initialized ⎯ Initialized ⎯ Initialized Initialized DADRB Initialized ⎯ Initialized ⎯ Initialized Initialized DACNT Initialized ⎯ Initialized ⎯ Initialized Initialized FCCS Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FPCS Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FECS Initialized ⎯ ⎯ ⎯ ⎯ ⎯ FKEY Initialized ⎯ ⎯ ⎯ ⎯ ⎯
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module KBCR1_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ PS2_3 KBTR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ICXR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ IIC_0 ICXR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ IIC_1 KBCRH_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ PS2_0 KBCRL_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ KBBR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ KBCR2_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ KBCRH_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ KBCRL_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ KBBR_
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module ISCR16L Initialized ⎯ ⎯ ⎯ ⎯ ⎯ INT ISSR16 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ISSR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ PCSR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ PWMX SBYCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ SYSTEM LPWRCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ MSTPCRH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ MSTPCRL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ SMR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ BRR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ SCR_1 Initialized ⎯ ⎯
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module P1DDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ PORT P2DDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P1DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P2DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P3DDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P4DDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P3DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P4DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P5DDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P6DDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P5DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ P6DR Initial
Section 27 List of Registers Reset HighSpeed/Medium speed Watch Sleep Module Stop Software Standby TCORA_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCORA_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCORB_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCORB_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCNT_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ TCNT_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ICCR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ICSR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ICDR_0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SARX_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ICMR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ SAR_0 Initialize
Section 27 List of Registers 27.
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'F944 P9PIN (Read) PORTS = 1 PORT H'F946 P9PCR H'F950 PADDR H'F951 PBDDR H'F952 PAODR H'F953 PBODR H'F954 PAPIN (Read) H'F955 PBPIN (Read) H'F957 PBPCR H'F960 PCDDR H'F961 PDDDR H'F962 PCODR H'F963 PDODR H'F964 PCPIN (Read) H'F965 PDPIN (Read) H'F966 PCPCR H'F967 PDPCR H'F968 PCNOCR H'F969 PDNOCR H'F96A PCNCE H'F96C PCNCMC H'F96E PCNCCS H'F971 PFDDR H'F97
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'F983 PHODR PORTS = 1 PORT H'F984 PGPIN (Read) H'F985 PHPIN (Read) H'F987 PHPCR H'F988 PGNOCR H'F989 PHNOCR H'F98A PGNCE H'F98C PGNCMC H'F98E PGNCCS H'F990 PIDDR H'F991 PJDDR H'F992 PIODR H'F993 PJODR H'F994 PIPIN (Read) H'F995 PJPIN (Read) H'F996 PIPCR H'F997 PJPCR H'F998 PINOCR H'F999 PJNOCR H'FA40 CCR1 H'FA41 CCR2 H'FA42 CSTR H'FA43 CEIR H'FA44 BRR H
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FA4F DT1MAX MSTPA3 = 0 CIR H'FA50 RMIN H'FA51 RMAX H'FB40 TDPCNT_0 MSTPA6 = 0 TDP_0 H'FB42 TDPWDMX_0 H'FB44 TDPWDMN_0 MSTPA5 = 0 TDP_1 MSTPA4 = 0 TDP_2 H'FB46 TDPPDMX_0 H'FB48 TDPICR_0 H'FB4A TDPICRF_0 H'FB4C TDPCSR_0 H'FB4D TDPCR1_0 H'FB4E TDPIER_0 H'FB4F TDPCR2_0 H'FB50 TDPPDMN_0 H'FB60 TDPCNT_1 H'FB62 TDPWDMX_1 H'FB64 TDPWDMN_1 H'FB66 TDPPDMX_1 H'FB68 TD
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FB8A TDPICRF_1 MSTPA4 = 0 TDP_2 H'FB8C TDPCSR_1 H'FB8D TDPCR1_1 H'FB8E TDPIER_1 H'FB8F TDPCR2_1 H'FB90 TDPPDMN_1 MSTPB1 = 0 TCM_0 MSTPB1 = 0 TCM_1 MSTPB2 = 0 TCM_2 H'FBC0 TCMCNT_0 H'FBC2 TCMMLCM_0 H'FBC4 TCMICR_0 H'FBC6 TCMICRF_0 H'FBC8 TCMCSR_0 H'FBC9 TCMCR_0 H'FBCA TCMIER_0 H'FBCC TCMMINCM_0 H'FBD0 TCMCNT_1 H'FBD2 TCMMLCM_1 H'FBD4 TCMICR_1 H'FBD6 TCMICRF_1
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FBF0 TCMCNT_3 MSTPB2 = 0 TCM_3 H'FBF2 TCMMLCM_3 H'FBF4 TCMICR_3 H'FBF6 TCMICRF_3 H'FBF8 TCMCSR_3 H'FBF9 TCMCR_3 MSTP9 = 0 A/D converter MSTPB3 = 0 SCIF H'FBFA TCMIER_3 H'FBFC TCMMINCM_3 H'FC00 ADDRA H'FC02 ADDRB H'FC04 ADDRC H'FC06 ADDRD H'FC08 ADDRE H'FC0A ADDRF H'FC0C ADDRG H'FC0E ADDRH H'FC10 ADCSR H'FC11 ADCR H'FC20 FRBR H'FC20 FTHR H'FC20 FDLL H'FC2
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FC50 FSIHBARH MSTP0 = 0 FSI H'FC51 FSIHBARL MSTPA2 = 0 H'FC52 FSISR H'FC53 CMDHBARH H'FC54 CMDHBARL H'FC55 FSICMDR H'FC56 FSILSTR1 H'FC57 FSIGPR1 H'FC58 FSIGPR2 H'FC59 FSIGPR3 H'FC5A FSIGPR4 H'FC5B FSIGPR5 H'FC5C FSIGPR6 H'FC5D FSIGPR7 H'FC5E FSIGPR8 H'FC5F FSIGPR9 H'FC60 FSIGPRA H'FC61 FSIGPRB H'FC62 FSIGPRC H'FC63 FSIGPRD H'FC64 FSIGPRE H'FC65 FSIGPRF H
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FC90 FSICR1 MSTP0 = 0 FSI H'FC91 FSICR2 MSTPA2 = 0 H'FC92 FSIBNR H'FC93 FSIINS H'FC94 FSIRDINS H'FC95 FSIPPINS H'FC96 FSISTR H'FC98 FSITDR0 H'FC99 FSITDR1 H'FC9A FSITDR2 H'FC9B FSITDR3 H'FC9C FSITDR4 H'FC9D FSITDR5 H'FC9E FSITDR6 H'FC9F FSITDR7 H'FCA0 FSIRDR H'FD00 PWMREG0_A H'FD01 PWMPRE0_A H'FD02 PWMREG1_A H'FD03 PWMPRE1_A H'FD04 PWMREG2_A H'FD05 PWMPRE2
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FD10 PWMREG0_B MSTPB0 = 0 PWMU_B H'FD11 PWMPRE0_B H'FD12 PWMREG1_B H'FD13 PWMPRE1_B H'FD14 PWMREG2_B H'FD15 PWMPRE2_B No condition SYSTEM MSTP1 = 0 TPU_1 H'FD16 PWMREG3_B H'FD17 PWMPRE3_B H'FD18 PWMREG4_B H'FD19 PWMPRE4_B H'FD1A PWMREG5_B H'FD1B PWMPRE5_B H'FD1C PWMCONA_B H'FD1D PWMCONB_B H'FD1E PWMCONC_B H'FD1F PWMCOND_B H'FD3A SYTSR0 H'FD3B SYTSR1 H'FD40 TC
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FDC0 LADR1H MSTP0 = 0 LPC H'FDC1 LADR1L H'FDC2 LADR2H H'FDC3 LADR2L H'FDC4 SCIFADRH H'FDC5 SCIFADRL H'FDD4 LADR4H H'FDD5 LADR4L H'FDD6 IDR4 H'FDD7 ODR4 H'FDD8 STR4 H'FDD9 HICR4 H'FDDA SIRQCR2 H'FDDB SIRQCR3 H'FE00 P6NCE PORTS = 0 PORT H'FE01 P6NCMC H'FE02 P6NCCS H'FE03 PCNCE H'FE04 PCNCMC H'FE05 PCNCCS H'FE06 PGNCE H'FE07 PGNCMC H'FE08 PGNCCS H'FE0C P
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FE10 PTCNT0 No condition PORT H'FE11 PTCNT1 H'FE12 PTCNT2 H'FE14 P9PCR H'FE16 PGNOCR H'FE19 PFNOCR H'FE1C PCNOCR H'FE1D PDNOCR H'FE20 TWR0MW TWR0SW H'FE21 TWR1 H'FE22 TWR2 H'FE23 TWR3 H'FE24 TWR4 H'FE25 TWR5 H'FE26 TWR6 H'FE27 TWR7 H'FE28 TWR8 H'FE29 TWR9 H'FE2A TWR10 H'FE2B TWR11 H'FE2C TWR12 H'FE2D TWR13 H'FE2E TWR14 H'FE2F TWR15 H'FE30 IDR3 H'FE31
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FE32 STR3 MSTP0 = 0 LPC H'FE33 HICR5 H'FE34 LADR3H H'FE35 LADR3L H'FE36 SIRQCR0 H'FE37 SIRQCR1 H'FE38 IDR1 H'FE39 ODR1 H'FE3A STR1 H'FE3B SIRQCR4 H'FE3C IDR2 H'FE3D ODR2 H'FE3E STR2 H'FE3F HISEL H'FE40 HICR0 H'FE41 HICR1 H'FE42 HICR2 H'FE43 HICR3 H'FE45 WUEMR No condition INT H'FE46 PGODR PORTS = 0 PORT H'FE47 PGPIN (Read) PGDDR (Write) H'FE49 PFODR H'
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FE50 TCR_0 MSTP1 = 0 TPU_0 H'FE51 TMDR_0 H'FE52 TIORH_0 H'FE53 TIORL_0 H'FE54 TIER_0 H'FE55 TSR_0 H'FE56 TCNT_0 H'FE58 TGRA_0 H'FE5A TGRB_0 H'FE5C TGRC_0 H'FE5E TGRD_0 H'FE70 TCR_2 H'FE71 TMDR_2 H'FE72 TIOR_2 TPU_2 H'FE74 TIER_2 H'FE75 TSR_2 H'FE76 TCNT_2 H'FE78 TGRA_2 H'FE7A TGRB_2 H'FE7D SYSCR3 H'FE7E MSTPCRA H'FE7F MSTPCRB H'FE81 KMIMR (RELOCATE = 1)
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FE88 ICCR_2 MSTPB4 = 0 IIC_2 H'FE89 ICSR_2 H'FE8A ICRES_2 H'FE8C ICXR_2 H'FE8E ICDR_2 ICE in ICCR_2 = 1 H'FE8E SARX_2 ICE in ICCR_2 = 0 H'FE8F ICMR_2 ICE in ICCR_2 = 1 H'FE8F SAR_2 ICE in ICCR_2 = 0 H'FEA0 DACR (RELOCATE = 1) MSTP11 = 0 MSTPA1 = 0 DADRAH (RELOCATE = 1) H'FEA1 DADRAL (RELOCATE = 1) H'FEA6 DADRBH (RELOCATE = 1) H'FEA7 REGS in PWMX DACNT/DADRB = 1 REGS in DA
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FEB0 TSTR MSTP1 = 0 TPU common H'FEB1 TSYR H'FEC0 KBCR1_0 MSTP2 = 0 PS2 H'FEC1 KBTR_0 H'FEC2 KBCR1_1 H'FEC3 KBTR_1 H'FEC4 KBCR1_2 H'FEC5 KBTR_2 H'FEC6 TCRXY MSTP8 = 0 TMR_XY H'FEC8 TCR_Y (RELOCATE = 1) H'FEC9 TCSR_Y (RELOCATE = 1) H'FECA TCORA_Y (RELOCATE = 1) H'FECB TCORB_Y (RELOCATE = 1) H'FECC TCNT_Y (RELOCATE = 1) H'FECE ICDR_1 (RELOCATE = 1) H'FECF MSTP3 = 0
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FED2 KBCR1_3 MSTPB5 PS2_3 H'FED3 KBTR_3 H'FED4 ICXR_0 MSTP4 = 0 IIC_0 H'FED5 ICXR_1 MSTP3 = 0 IIC_1 H'FED8 KBCRH_0 MSTP2 = 0 PS2 H'FED9 KBCRL_0 H'FEDA KBBR_0 H'FEDB KBCR2_0 H'FEDC KBCRH_1 H'FEDD KBCRL_1 H'FEDE KBBR_1 H'FEDF KBCR2_1 H'FEE0 KBCRH_2 H'FEE1 KBCRL_2 H'FEE2 KBBR_2 H'FEE3 KBCR2_2 H'FEE6 ICRES_0 MSTP4 = 0, IICE in STCR = 1 IIC_0 H'FEE8 ICRA No con
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FEFC ISSR16 No condition INT H'FEFD ISSR H'FF82 PCSR (RELOCATE = 0) FLSHE in STCR = 0 PWMX PCSR (RELOCATE = 1) No condition SBYCR (RELOCATE = 0) FLSHE in STCR = 0 SBYCR (RELOCATE = 1) No condition LPWRCR (RELOCATE = 0) FLSHE in STCR = 0 LPWRCR (RELOCATE = 1) No condition MSTPCRH (RELOCATE = 0) FLSHE in STCR = 0 MSTPCRH (RELOCATE = 1) No condition MSTPCRL (RELOCATE = 0) FLSHE i
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FF8A SCR_1 MSTP6 = 0 SCI_1 H'FF8B TDR_1 H'FF8C SSR_1 H'FF8D RDR_1 H'FF8E SCMR_1 (RELOCATE = 1) MSTP6 = 0 SCMR_1 (RELOCATE = 0) MSTP6 = 0, IICE in STCR = 0 ICDR_1 (RELOCATE = 0) MSTP3 = 0 ICE in ICCR_1 = 1 IICE in STCR = 1 ICE in ICCR_1 = 0 SARX_1 (RELOCATE = 0) H'FF8F H'FFA0 ICMR_1 (RELOCATE = 0) ICE in ICCR_1 = 1 SAR_1 (RELOCATE = 0) ICE in ICCR_1 = 0 MSTP11 = 0 REGS in DACNT/ M
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FFA5 RDR_2 MSTP5 = 0 SCI_2 H'FFA6 SCMR_2 H'FFA7 DADRBL (RELOCATE = 0) DACNTL (RELOCATE = 0) H'FFA8 TCSR_0 MSTP11 = 0 MSTPA1 = 0 IICE in STCR = 1 REGS in DACNT/ DADRB = 0 PWMX REGS in DACNT/ DADRB = 1 No condition WDT_0 PORTS = 0 PORT TCNT_0 (Write) H'FFA9 TCNT_0 (Read) H'FFAA PAODR H'FFAB PAPIN (Read) PADDR (Write) H'FFAC P1PCR H'FFAD P2PCR H'FFAE P3PCR H'FFB0 P1DDR H'F
Section 27 List of Registers Lower Address Register Abbreviation Register Selection Condition Module H'FFBE P7PIN (Read) PORTS = 0 PORT PBDDR (Write) H'FFBF P8DR H'FFC0 P9DDR H'FFC1 P9DR H'FFC2 IER No condition INT H'FFC3 STCR No condition SYSTEM H'FFC4 SYSCR H'FFC5 MDCR H'FFC6 BCR No condition BSC H'FFC7 WSCR H'FFC8 TCR_0 MSTP12 = 0 TMR_0, TMR_1 H'FFC9 TCR_1 H'FFCA TCSR_0 H'FFCB TCSR_1 H'FFCC TCORA_0 H'FFCD TCORA_1 H'FFCE TCORB_0 H'FFCF TCORB_1 H'FFD8 ICC
Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FFE0 KBCRH_3 MSTPB5 = 0 PS2_3 H'FFE1 KBCRL_3 H'FFE2 KBBR_3 H'FFE3 KBCR2_3 H'FFEA TCSR_1 No condition WDT_1 TMR_X TCNT_1 (Write) H'FFEB TCNT_1 (Read) H'FFF0 TCR_X (RELOCATE = 1) MSTP8 = 0 TCR_X (RELOCATE = 0) MSTP8 = 0 TMRX/Y KINWUE in SYSCR = 0 in TCONRS = 0 TCR_Y (RELOCATE = 0) TMRX/Y in TCONRS = 1 H'FFF1 H'FFF2 KMIMR (RELOCATE = 0) MSTP2 = 0 KINWUE in SYSCR = 1 INT TCSR_X
Section 27 List of Registers Register Lower Address Abbreviation Register Selection Condition Module H'FFF3 KMIMRA (RELOCATE = 0) MSTP2 = 0, KINWUE in SYSCR = 1 INT TICRF (RELOCATE = 1) MSTP8 = 0 TMR_X TICRF (RELOCATE = 0) MSTP8 = 0 TMRX/Y KINWUE in SYSCR = 0 in TCONRS = 0 TCORB_Y (RELOCATE = 0) TMRX/Y in TCONRS = 1 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFFC H'FFFE TCNT_X (RELOCATE = 1) MSTP8 = 0 TCNT_X (RELOCATE = 0) MSTP8 = 0 TMRX/Y KINWUE in SYSCR = 0 in TCONRS = 0 TCNT_Y (RELOCATE = 0)
Section 27 List of Registers 27.
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States BSC BCR 8 H'FFC6 8 2 BSC WSCR 8 H'FFC7 8 2 PORT P1DDR 8 H'F900 (PORTS = 1) 8 2 PORT P2DDR 8 H'F901 (PORTS = 1) 8 2 PORT P1DR 8 H'F902 (PORTS = 1) 8 2 PORT P2DR 8 H'F903 (PORTS = 1) 8 2 PORT P1PIN 8 H'F904 (Read) (PORTS = 1) 8 2 PORT P2PIN 8 H'F905 (Read) (PORTS = 1) 8 2 PORT P1PCR 8 H'F906 (PORTS = 1) 8 2 PORT P2PCR 8 H'F907 (PORTS = 1)
Section 27 List of Registers Data Bus Width Access States H'F922 (PORTS = 1) 8 2 8 H'F923 (PORTS = 1) 8 2 P5PIN 8 H'F924 (Read) (PORTS = 1) 8 2 PORT P6PIN 8 H'F925 (Read) (PORTS = 1) 8 2 PORT P6NCE 8 H'F92B (PORTS = 1) 8 2 PORT P6NCMC 8 H'F92D (PORTS = 1) 8 2 PORT P6NCCS 8 H'F92F (PORTS = 1) 8 2 PORT P8DDR 8 H'F931 (PORTS = 1) 8 2 PORT P8DR 8 H'F933 (PORTS = 1) 8 2 PORT P7PIN 8 H'F934 (Read) (PORTS = 1) 8 2 PORT P8PIN 8 H'F935 (Read) (PORTS = 1) 8
Section 27 List of Registers Data Bus Width Access States H'F953 (PORTS = 1) 8 2 8 H'F954 (Read) (PORTS = 1) 8 2 PBPIN 8 H'F955 (Read) (PORTS = 1) 8 2 PORT PBPCR 8 H'F957 (PORTS = 1) 8 2 PORT PCDDR 8 H'F960 (PORTS = 1) 8 2 PORT PDDDR 8 H'F961 (PORTS = 1) 8 2 PORT PCODR 8 H'F962 (PORTS = 1) 8 2 PORT PDODR 8 H'F963 (PORTS = 1) 8 2 PORT PCPIN 8 H'F964 (Read) (PORTS = 1) 8 2 PORT PDPIN 8 H'F965 (Read) (PORTS = 1) 8 2 PORT PCPCR 8 H'F966 (PORTS = 1) 8
Section 27 List of Registers Data Bus Width Access States H'F973 (PORTS = 1) 8 2 8 H'F974 (Read) (PORTS = 1) 8 2 PFPIN 8 H'F975 (Read) (PORTS = 1) 8 2 PORT PFPCR 8 H'F977 (PORTS = 1) 8 2 PORT PFNOCR 8 H'F979 (PORTS = 1) 8 2 PORT PGDDR 8 H'F980 (PORTS = 1) 8 2 PORT PHDDR 8 H'F981 (PORTS = 1) 8 2 PORT PGODR 8 H'F982 (PORTS = 1) 8 2 PORT PHODR 8 H'F983 (PORTS = 1) 8 2 PORT PGPIN 8 H'F984 (Read) (PORTS = 1) 8 2 PORT PHPIN 8 H'F985 (Read) (PORTS = 1) 8
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States PORT PIODR 8 H'F992 8 2 PORT PJODR 8 H'F993 8 2 PORT PIPIN 8 H'F994 (Read) 8 2 PORT PJPIN 8 H'F995 (Read) 8 2 PORT PJPCR 8 H'F997 8 2 PORT PINOCR 8 H'F998 8 2 PORT PJNOCR 8 H'F999 8 2 PORT P6NCE 8 H'FE00 (PORTS = 0) 8 2 PORT P6NCMC 8 H'FE01 (PORTS = 0) 8 2 PORT P6NCCS 8 H'FE02 (PORTS = 0) 8 2 PORT PCNCE 8 H'FE03 (PORTS = 0) 8 2
Section 27 List of Registers Data Bus Width Access States H'FE10 (PORTS = 0) 8 2 8 H'FE11 (PORTS = 0) 8 2 PTCNT2 8 H'FE12 (PORTS = 0) 8 2 PORT P9PCR 8 H'FE14 (PORTS = 0) 8 2 PORT PGNOCR 8 H'FE16 (PORTS = 0) 8 2 PORT PFNOCR 8 H'FE19 (PORTS = 0) 8 2 PORT PCNOCR 8 H'FE1C (PORTS = 0) 8 2 PORT PDNOCR 8 H'FE1D (PORTS = 0) 8 2 PORT PGODR 8 H'FE46 (PORTS = 0) 8 2 PORT PGPIN 8 H'FE47 (Read) (PORTS = 0) 8 2 PORT PGDDR 8 H'FE47 (Write) (PORTS = 0) 8 2 PORT
Section 27 List of Registers Data Bus Width Access States H'FE4C (PORTS = 0) 8 2 8 H'FE4D (PORTS = 0) 8 2 PCPIN 8 H'FE4E (Read) (PORTS = 0) 8 2 PORT PCDDR 8 H'FE4E (Write) (PORTS = 0) 8 2 PORT PDPIN 8 H'FE4F (Read) (PORTS = 0) 8 2 PORT PDDDR 8 H'FE4F (Write) (PORTS = 0) 8 2 PORT KMPCR 8 H'FE82 8 (RELOCATE = 1) (PORTS = 0) 2 PORT PAODR 8 H'FFAA (PORTS = 0) 8 2 PORT PAPIN 8 H'FFAB (Read) (PORTS = 0) 8 2 PORT PADDR 8 H'FFAB (Write) (PORTS = 0) 8 2 PORT P
Section 27 List of Registers Data Bus Width Access States H'FFB3 (PORTS = 0) 8 2 8 H'FFB4 (PORTS = 0) 8 2 P4DDR 8 H'FFB5 (PORTS = 0) 8 2 PORT P3DR 8 H'FFB6 (PORTS = 0) 8 2 PORT P4DR 8 H'FFB7 (PORTS = 0) 8 2 PORT P5DDR 8 H'FFB8 (PORTS = 0) 8 2 PORT P6DDR 8 H'FFB9 (PORTS = 0) 8 2 PORT P5DR 8 H'FFBA (PORTS = 0) 8 2 PORT P6DR 8 H'FFBB (PORTS = 0) 8 2 PORT PBODR 8 H'FFBC (PORTS = 0) 8 2 PORT P8DDR 8 H'FFBD (Write) (PORTS = 0) 8 2 PORT PBPIN 8 H'FF
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States TDP_0 TDPCNT_0 8 H'FB40 8 2 TDP_0 TDPWDMX_0 8 H'FB42 8 2 TDP_0 TDPWDMN_0 8 H'FB44 8 2 TDP_0 TDPPDMX_0 8 H'FB46 8 2 TDP_0 TDPICR_0 8 H'FB48 8 2 TDP_0 TDPICRF_0 8 H'FB8A 8 2 TDP_0 TDPCSR_0 8 H'FB8C 8 2 TDP_0 TDPCR1_0 8 H'FB4D 8 2 TDP_0 TDPIER_0 8 H'FB4E 8 2 TDP_0 TDPCR2_0 8 H'FB4F 8 2 TDP_0 TDPPDMN_0 16 H'FB50 16 2 TDP_1 TDPCNT_
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States TDP_2 TDPCR2_2 8 H'FB8F 8 2 TDP_2 TDPPDMN_2 16 H'FB90 16 2 TCM_0 TCMCNT_0 16 H'FBC0 16 2 TCM_0 TCMMLCM_0 16 H'FBC2 16 2 TCM_0 TCMICR_0 16 H'FBC4 16 2 TCM_0 TCMICRF_0 16 H'FBC6 16 2 TCM_0 TCMCSR_0 8 H'FBC8 8 2 TCM_0 TCMCR_0 8 H'FBC9 8 2 TCM_0 TCMIER_0 8 H'FBCA 8 2 TCM_0 TCMMINCM_0 16 H'FBCC 16 2 TCM_1 TCMCNT_1 16 H'FBD0 16 2 TCM_
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States TCM_3 TCMCR_3 8 H'FBF9 8 2 TCM_3 TCMIER_3 8 H'FBFA 8 2 TCM_3 TCMMINCM_3 16 H'FBFC 16 2 FSI FSIHBARH 8 H'FC50 8 2 FSI FSIHBARL 8 H'FC51 8 2 FSI FSISR 8 H'FC52 8 2 FSI CMDHBARH 8 H'FC53 8 2 FSI CMDHBARH 8 H'FC54 8 2 FSI FSICMDR 8 H'FC55 8 2 FSI FSILSTR1 8 H'FC56 8 2 FSI FSIGPR1 8 H'FC57 8 2 FSI FSIGPR2 8 H'FC58 8 2 FSI FSIG
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States FSI FSIWDRLH 8 H'FC6C 8 2 FSI FSIWDRLL 8 H'FC6D 8 2 FSI FSILSTR2 8 H'FC6E 8 2 FSI FSICR1 8 H'FC90 8 2 FSI FSICR2 8 H'FC91 8 2 FSI FSIBNR 8 H'FC92 8 2 FSI FSINS 8 H'FC93 8 2 FSI FSIRDINS 8 H'FC94 8 2 FSI FSIPPINS 8 H'FC95 8 2 FSI FSISTR 8 H'FC96 8 2 FSI FSITDR0 8 H'FC98 8 2 FSI FSITDR1 8 H'FC99 8 2 FSI FSITDR2 8 H'FC9A
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States CIR DT1MIN 8 H'FA4E 8 2 CIR DT1MAX 8 H'FA4F 8 2 CIR RMIN 8 H'FA50 8 2 CIR RMAX 8 H'FA51 8 2 PWMU_A PWMREG0 8 H'FD00 8 2 PWMU_A PWMPRE0 8 H'FD01 8 2 PWMU_A PWMREG1 8 H'FD02 8 2 PWMU_A PWMPRE1 8 H'FD03 8 2 PWMU_A PWMREG2 8 H'FD04 8 2 PWMU_A PWMPRE2 8 H'FD05 8 2 PWMU_A PWMREG3 8 H'FD06 8 2 PWMU_A PWMPRE3 8 H'FD07 8 2 PWMU_A
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States PWMU_B PWMCONA 8 H'FD1C 8 2 PWMU_B PWMCONB 8 H'FD1D 8 2 PWMU_B PWMCONC 8 H'FD1E 8 2 PWMU_B PWMCOND 8 H'FD1F 8 2 PWMX DACR 8 H'FEA0 (RELOCATE = 1) 8 2 PWMX DADRAH 8 H'FEA0 8 (RELOCATE = 1) 2 PWMX DADRAL 8 H'FEA1 8 (RELOCATE = 1) 2 PWMX DADRBH 8 H'FEA6 8 (RELOCATE = 1) 2 PWMX DACNTH 8 H'FEA6 8 (RELOCATE = 1) 2 PWMX DADRBL 8 H'FEA7 8 (RELOCATE
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States TPU_0 TIORH_0 8 H'FE52 8 2 TPU_0 TIORL_0 8 H'FE53 8 2 TPU_0 TIER_0 8 H'FE54 8 2 TPU_0 TSR_0 8 H'FE55 8 2 TPU_0 TCNT_0 16 H'FE56 16 2 TPU_0 TGRA_0 16 H'FE58 16 2 TPU_0 TGRB_0 16 H'FE5A 16 2 TPU_0 TGRC_0 16 H'FE5C 16 2 TPU_0 TGRD_0 16 H'FE5E 16 2 TPU_1 TCR_1 8 H'FD40 8 2 TPU_1 TMDR_1 8 H'FD41 8 2 TPU_1 TIOR_1 8 H'FD42 8 2 T
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States TMR_0 TCORB_0 8 H'FFCE 16 2 TMR_0 TCNT_0 8 H'FFD0 16 2 TMR_1 TCR_1 8 H'FFC9 8 2 TMR_1 TCSR_1 8 H'FFCB 16 2 TMR_1 TCORA_1 8 H'FFCD 16 2 TMR_1 TCORB_1 8 H'FFCF 16 2 TMR_1 TCNT_1 8 H'FFD1 16 2 TMR_X TCR_X 8 H'FFF0 8 2 TMR_X TCSR_X 8 H'FFF1 8 2 TMR_X TICRR 8 H'FFF2 8 2 TMR_X TICRF 8 H'FFF3 8 2 TMR_X TCNT_X 8 H'FFF4 8 2 TMR_X
Section 27 List of Registers Data Bus Width Access States Module Register Abbreviation Number of Bits TMR_Y TCNT_Y 8 H'FFF4 8 (RELOCATE = 0) 2 TMR_XY TCRXY 8 H'FEC6 2 TMR_X TCONRI 8 H'FFFC 8 2 TMR_X, TMR_Y TCONRS 8 H'FFFE 8 2 WDT_0 TCSR_0 8 H'FFA8 (Write) 16 2 WDT_0 TCSR_0 8 H'FFA8 (Read) 8 2 WDT_0 TCNT_0 8 H'FFA8 (Write) 16 2 WDT_0 TCNT_0 8 H'FFA9 (Read) 8 2 WDT_1 TCSR_1 8 H'FFEA (Write) 16 2 WDT_1 TCSR_1 8 H'FFEA (Read) 8 2 WDT_1 TCNT_1 8
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States IIC_0 SARX_0 8 H'FFDE 8 2 IIC_0 ICMR_0 8 H'FFDF 8 2 IIC_0 SAR_0 8 H'FFDF 8 2 IIC_1 ICDR_1 8 H'FECE 8 (RELOCATE = 1) 2 IIC_1 SARX_1 8 H'FECE 8 (RELOCATE = 1) 2 IIC_1 ICMR_1 8 H'FECF 8 (RELOCATE = 1) 2 IIC_1 SAR_1 8 H'FECF 8 (RELOCATE = 1) 2 IIC_1 ICCR_1 8 H'FED0 8 (RELOCATE = 1) 2 IIC_1 ICSR_1 8 H'FED1 8 (RELOCATE = 1) 2 IIC_1 ICXR_1 8 H'FED5
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States IIC_2 ICMR_2 8 H'FE8F 8 2 IIC_2 SAR_2 8 H'FE8F 8 2 IIC_0 ICRES_0 8 H'FEE6 8 2 PS2_0 KBCR1_0 8 H'FEC0 8 2 PS2_0 KBTR_0 8 H'FEC1 8 2 PS2_0 KBCRH_0 8 H'FED8 8 2 PS2_0 KBCRL_0 8 H'FED9 8 2 PS2_0 KBBR_0 8 H'FEDA 8 2 PS2_0 KBCR2_0 8 H'FEDB 8 2 PS2_1 KBCR1_1 8 H'FEC2 8 2 PS2_1 KBTR_1 8 H'FEC3 8 2 PS2_1 KBCRH_1 8 H'FEDC 8 2 PS2_1
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States LPC SCIFADRH 8 H'FDC4 8 2 LPC SCIFADRL 8 H'FDC5 8 2 LPC LADR4H 8 H'FDD4 8 2 LPC LADR4L 8 H'FDD5 8 2 LPC IDR4 8 H'FDD6 8 2 LPC ODR4 8 H'FDD7 8 2 LPC STR4 8 H'FDD8 8 2 LPC HICR4 8 H'FDD9 8 2 LPC SIRQCR2 8 H'FDDA 8 2 LPC SIRQCR3 8 H'FDDB 8 2 LPC TWR0MW 8 H'FE20 8 2 LPC TWR0SW 8 H'FE20 8 2 LPC TWR1 8 H'FE21 8 2 LPC TWR
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States LPC LADR3H 8 H'FE34 8 2 LPC LADR3L 8 H'FE35 8 2 LPC SIRQCR0 8 H'FE36 8 2 LPC SIRQCR1 8 H'FE37 8 2 LPC IDR1 8 H'FE38 8 2 LPC ODR1 8 H'FE39 8 2 LPC STR1 8 H'FE3A 8 2 LPC SIRQCR4 8 H'FE3B 8 2 LPC IDR2 8 H'FE3C 8 2 LPC ODR2 8 H'FE3D 8 2 LPC STR2 8 H'FE3E 8 2 LPC HISEL 8 H'FE3F 8 2 LPC HICR0 8 H'FE40 8 2 LPC HICR1 8 H
Section 27 List of Registers Module Register Abbreviation Number of Bits Address Data Bus Width Access States SCIF FFCR 8 H'FC22 8 2 SCIF FLCR 8 H'FC23 8 2 SCIF FMCR 8 H'FC24 8 2 SCIF FLSR 8 H'FC25 8 2 SCIF FMSR 8 H'FC26 8 2 SCIF FSCR 8 H'FC27 8 2 SCIF SCIFCR 8 H'FC28 8 2 ROM FCCS 8 H'FEA8 8 2 ROM FPCS 8 H'FEA9 8 2 ROM FECS 8 H'FEAA 8 2 ROM FKEY 8 H'FEAC 8 2 ROM FMATS 8 H'FEAD 8 2 ROM FTDAR 8 H'FEAE 8 2 SYSTEM SYSCR3 8 H
Section 28 Electrical Characteristics Section 28 Electrical Characteristics 28.1 Absolute Maximum Ratings Table 28.1 lists the absolute maximum ratings. Table 28.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* VCC –0.3 to +4.3 V Input voltage (except ports 7, D, A, G, I, PE4, PE2 to PE0, P97, P86, P52, and P42) Vin –0.3 to VCC + 0.3 Input voltage (ports A, G, I, PE4, PE2 to PE0, Vin P97, P86, P52, and P42) –0.3 to +7.
Section 28 Electrical Characteristics 28.2 DC Characteristics Table 28.2 lists the DC characteristics. Table 28.3 lists the permissible output currents. Table 28.4 lists the bus drive characteristics. Table 28.2 DC Characteristics (1) 1 1 Conditions: VCC = 3.0 V to 3.6 V, AVCC* = 3.0 V to 3.6 V, AVref* = 3.0 V to AVCC, 1 VSS = AVSS* = 0 V Test Item Symbol Conditions Min. Typ. Max. Unit VCC × 0.2 ⎯ ⎯ V V T+ ⎯ ⎯ VCC × 0.7 V T+ – VT– VCC × 0.05 ⎯ ⎯ VI H VCC × 0.9 ⎯ VCC + 0.
Section 28 Electrical Characteristics Table 28.2 DC Characteristics (2) 1 1 Conditions: VCC = 3.0 V to 3.6 V, AVCC* = 3.0 V to 3.6 V, AVref* = 3.0 V to AVCC, 1 VSS = AVSS* = 0 V Item Symbol Min. Input leakage RES current NMI, MD2, MD1, ETRST | Iin | Typ. Max. Unit Test Conditions ⎯ ⎯ 10.0 µA Vin = 0.5 to ⎯ ⎯ 1.0 ⎯ ⎯ 1.0 Vin = 0.5 to AVCC – 0.5 V ⎯ ⎯ 1.0 Vin = 0.5 to VCC – 0.
Section 28 Electrical Characteristics Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a value in the range from 3.0 V to 3.6 V to the AVCC and AVref pins by connecting to the power supply (VCC). The relationship between these two pins should be AVref ≤ AVCC. 2. Ports A, G, I, P97, P86, P52, P42, and peripheral module outputs multiplexed on the pin are NMOS push-pull outputs.
Section 28 Electrical Characteristics Table 28.2 DC Characteristics (4) Using FSI Function Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V Item Symbol Min. Typ. Max. Unit Test Conditions VIH VCC × 0.7 ⎯ VCC + 0.3 V ⎯ Input low voltage VIL − 0.3 ⎯ VCC × 0.2 ⎯ Output high voltage VOH VCC − 0.5 ⎯ ⎯ IOH = −200 μA VCC − 1.0 ⎯ ⎯ IOH = −1 mA Output low voltage VOL ⎯ ⎯ 0.4 IOL = 1.
Section 28 Electrical Characteristics Table 28.4 Bus Drive Characteristics Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V Applicable Pins: SCL0, SDA0, SCL1, SDA1, SCL2, SDA2, ExSCLA, ExSDAA, ExSCLB, and ExSDAB (bus drive function selected) Item Symbol Min. Schmitt trigger input voltage – VT + VT Typ. Max. Unit VCC × 0.3 ⎯ ⎯ V ⎯ ⎯ VCC × 0.7 Test Conditions VT – VT VCC × 0.05 ⎯ ⎯ Input high voltage VI H VCC × 0.7 ⎯ 5.5 Input low voltage VIL –0.5 ⎯ VCC × 0.
Section 28 Electrical Characteristics This LSI 600 Ω Ports 1 to 3, C and D LED Figure 28.2 LED Drive Circuit (Example) 28.3 AC Characteristics Figure 28.3 shows the test conditions for the AC characteristics. 3V RL LSI output pin C RH C = 30pF : All ports RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level : 0.8 V • High level : 1.5 V Figure 28.3 Output Load Circuit Rev. 2.00 Sep.
Section 28 Electrical Characteristics 28.3.1 Clock Timing Table 28.5 shows the clock timing. The clock timing specified here covers clock output (φ) and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 25, Clock Pulse Generator. Table 28.5 Clock Timing Condition A: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 8 MHz to 10 MHz Condition B: VCC = 3.0 V to 3.
Section 28 Electrical Characteristics EXTAL tDEXT VCC tOSC1 RES φ Figure 28.5 Oscillation Stabilization Timing φ NMI IRQi ( i = 0 to 15 ) KINi ( i = 0 to 15 ) WUEi ( i = 8 to 15 ) PS2AC to PS2DC tOSC2 Figure 28.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) Rev. 2.00 Sep.
Section 28 Electrical Characteristics 28.3.2 Control Signal Timing Table 28.6 shows the control signal timing. Only external interrupts NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD can be operated based on the subclock (φ = 32.768 kHz). Table 28.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 32.768 kHz, 8 MHz to maximum operating frequency Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 200 ⎯ ns Figure 28.
Section 28 Electrical Characteristics φ tNMIS tNMIH NMI tNMIW IRQi (i = 0 to 15) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input tIRQS tIRQH KINi (i = 0 to 15) WUEi (i = 8 to 15) tIRQW Figure 28.8 Interrupt Input Timing Rev. 2.00 Sep.
Section 28 Electrical Characteristics 28.3.3 Timing of On-Chip Peripheral Modules Table 28.7 shows the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock (φ = 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD) and watchdog timer (WDT_1) only. The system clock or LCLK operation can be used in the FSI. Table 28.7 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.
Section 28 Electrical Characteristics Symbol Min. Max. Unit Test Conditions Input clock rise time tSCKr ⎯ 1.5 tcyc Figure 28.20 Input clock fall time tSCKf ⎯ 1.5 Transmit data delay time (synchronous) tTXD ⎯ 50 ns Figure 28.21 Receive data setup time (synchronous) tRXS 50 ⎯ Receive data hold time (synchronous) tRXH 50 ⎯ ns Figure 28.
Section 28 Electrical Characteristics φ tTOCD Output compare outputs* tTICS Input capture inputs* Note: * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, and TIOCD0 Figure 28.10 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWH tTCKWL Figure 28.11 TPU Clock Input Timing φ tTMOD TMO_0, TMO_1 TMO_X, TMO_Y Figure 28.12 8-Bit Timer Output Timing φ tTMCS tTMCS TMI_0, TMI_1 TMI_X, TMI_Y tTMCWL tTMCWH Figure 28.13 8-Bit Timer Clock Input Timing Rev. 2.00 Sep.
Section 28 Electrical Characteristics φ tTMRS TMI_0, TMI_1 TMI_X, TMI_Y Figure 28.14 8-Bit Timer Reset Input Timing φ tTCMS TCMCYI TCMMCI Figure 28.15 TCM Input Setup Time φ tTCMCKS TCMCKI tTCMCKW tTCMCKW Figure 28.16 TCM Clock Input Timing φ tTDPS TDPCYI TDPMCI Figure 28.17 TDP Input Setup Time Rev. 2.00 Sep.
Section 28 Electrical Characteristics φ tTDPCKS TDPCKI tTDPCKW tTDPCKW Figure 28.18 TDP Clock Input Timing φ tPWOD PWMU5A to PWMU0A, PWMU5B to PWMU0B, PWX1, PWX0 Figure 28.19 PWMU, PWMX Output Timing tSCKW tSCKr tSCKf SCK1 tScyc Figure 28.20 SCK Clock Input Timing SCK1 tTXD TxD1 (transmit data) tRXS tRXH RxD1 (receive data) Figure 28.21 SCI Input/Output Timing (Clock Synchronous Mode) Rev. 2.00 Sep.
Section 28 Electrical Characteristics tCKH tCYC FSICK tCKL FSICK tSSL tSSH FSISS tTXD FSIDO tRXS tRXH FSIDI Figure 28.22 FSI Input/Output Timing Table 28.8 PS2 Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 8 MHz to maximum operating frequency Standard Value Typ. Max. Test Unit Conditions Remarks ⎯ ⎯ 250 ns tKBIH 150 ⎯ ⎯ KCLK, KD input data setup time tKBIS 150 ⎯ ⎯ KCLK, KD output delay time tKBOD ⎯ ⎯ 450 KCLK, KD capacitive load Cb ⎯ ⎯ 400 Item Symbol Min.
Section 28 Electrical Characteristics (1) Receive φ tKBIS tKBIH KCLK/KD* (2) Transmit (a) φ tKBOD KCLK/KD* Transmit (b) KCLK/KD* tKBF Note: * KCLK : PS2AC to PS2DC KD : PS2AD to PS2DD Figure 28.23 PS2 Timing Rev. 2.00 Sep.
Section 28 Electrical Characteristics 2 Table 28.9 I C Bus Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 8 MHz to maximum operating frequency Item Symbol Min. Typ. Max. Unit SCL input cycle time tSCL 12 ⎯ ⎯ tcyc SCL input high pulse width tSCLH 3 ⎯ ⎯ SCL input low pulse width tSCLL 5 ⎯ ⎯ SCL, SDA input rise time tSr ⎯ ⎯ 7.
Section 28 Electrical Characteristics Table 28.10 LPC Timing Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V, φ = 8 MHz to maximum operating frequency, Ta = –20 to +75°C Item Symbol Min. Typ. Max.
Section 28 Electrical Characteristics Test voltage: 0.4Vcc 50 pF Figure 28.26 Test Conditions for Tester Table 28.11 JTAG Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 8 MHz to 20 MHz Test Conditions Item Symbol Min. Max. Unit ETCK clock cycle time tTCKcyc 50* 125* ns ETCK clock high pulse width tTCKH 20 ⎯ Figure 28.
Section 28 Electrical Characteristics tTCKcyc tTCKf tTCKH ETCK tTCKL tTCKr Figure 28.27 JTAG ETCK Timing ETCK tRSTHW RES ETRST tTRSTW Figure 28.28 Reset Hold Timing ETCK tTMSS tTMSH tTDIS tTDIH ETMS ETDI tTDOD ETDO Figure 28.29 JTAG Input/Output Timing Rev. 2.00 Sep.
Section 28 Electrical Characteristics 28.4 A/D Conversion Characteristics Table 28.12 lists the A/D conversion characteristics. Table 28.12 A/D Conversion Characteristics (AN15 to AN0 Input: 134/266-State Conversion) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 20 MHz Condition Item Min. Typ. Max. Resolution 10 Conversion time ⎯ ⎯ 4.
Section 28 Electrical Characteristics 28.5 Flash Memory Characteristics Table 28.13 lists the flash memory characteristics. Table 28.13 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Avref = 3.0 V to AVCC, VSS = AVSS = 0 V Ta = 0°C to +75°C (operating temperature range for programming/erasing) Item Symbol Min. Typ. Max.
Section 28 Electrical Characteristics 28.6 Usage Notes It is necessary to connect a bypass capacitor between the VCC pin and VSS pin, and a capacitor between the VCL pin and VSS pin for stable internal step-down power. An example of connection is shown in figure 28.30. Vcc power supply Bypass capacitor 10 µF External capacitor for internal step-down power stabilization VCC VCL One 0.1 μF / 0.47 μF or two in parallel 0.01 µF VSS It is recommended that a bypass capacitor be connected to the VCC pin.
Section 28 Electrical Characteristics Rev. 2.00 Sep.
Appendix Appendix A. I/O Port States in Each Pin State Table A.
Appendix B. Product Lineup Product Type Type Code H8S/2117R Flash memory version R4F2117R Rev. 2.00 Sep.
144 e 1 ZD y *3 Index mark D HD bp 36 73 F 37 72 x ZE M E *2 109 108 *1 Previous Code TFP-144/TFP-144V MASS[Typ.] 0.6g Detail F L1 L Terminal cross section b1 bp θ 17.8 HE 0.13 bp θ L 1.0 1.0 0.5 ZE L1 1.0 ZD 0.6 0.07 8° 0.08 0.4 y 0.4 0° 0.22 0.23 0.15 1.20 18.2 18.2 Max x e 0.15 0.17 c c1 0.16 0.18 0.10 b1 0.12 0.05 A1 A 18.0 17.8 HD 18.0 16 1.00 A2 16 Nom Dimension in Millimeters Min E D Reference Symbol NOTE) 1.
Appendix JEITA Package Code P-LFBGA176-13x13-0.80 RENESAS Code PLBG0176GA-A Previous Code BP-176/BP-176V MASS[Typ.] 0.45g D w S A E w S B x4 v y1 S A1 A S y S e ZD A Reference Dimension in Millimeters Symbol Min Nom Max e R P N M B L K J D 13.0 E 13.0 v 0.15 w 0.20 1.40 H A G A1 F E e D b ZE C B A 1 2 3 4 5 6 7 φb 8 REJ09B0452-0200 0.45 0.45 0.50 0.55 0.08 y 0.10 y1 0.2 SD φx M S A B SE Rev. 2.00 Sep. 28, 2009 Page 986 of 994 0.40 0.
Appendix JEITA Package Code P-TFLGA145-9x9-0.65 RENESAS Code PTLG0145JB-A Previous Code - MASS[Typ.] 0.15g D w S B E w S A x4 v y1 S A S y S e A ZD e N M L K J B H G F E D ZE C B Reference Symbol Dimension in Millimeters Min 9.0 E 9.0 1 2 3 4 5 6 7 φb 8 9 10 11 12 13 φxn S A B Max v 0.15 w 0.20 A 1.2 A1 0.65 e A Nom D b 0.30 0.35 x 0.40 0.08 y 0.1 y1 0.20 SD SE ZD 0.6 ZE 0.6 Figure C.3 Package Dimensions (TLP-145V) Rev. 2.00 Sep.
Appendix D. Treatment of Unused Pins The treatments of unused pins are listed in table D.1. Table D.
Index Numerics C 14-bit PWM timer (PWMX)................... 219 16-bit count mode ................................... 380 16-bit cycle measurement timer (TCM) . 305 16-bit timer pulse unit............................. 237 8-bit timer (TMR) ................................... 355 Cascaded connection............................... 380 Clock pulse generator.............................. 833 Clocked synchronous mode .................... 441 CMIA ......................................................
F Flash erase block select parameter.......... 775 Flash memory ................................. 329, 749 Flash multipurpose address area parameter ................................................ 774 Flash multipurpose data destination parameter ................................................ 774 Flash pass and fail parameter.................. 768 Flash program/erase frequency parameter ................................................ 773 FOVI.......................................................
OVI ......................................................... 384 P Parity error.............................................. 431 Pin arrangement in each operating mode.. 12 Pin assignments .......................................... 9 Pin functions ............................................. 19 Power-down modes ................................ 841 Program counter (PC) ............................... 39 program-counter relative .......................... 59 Programmer mode ..........................
KBBR ................................................. 598 KBCR1 ............................................... 591 KBCR2 ............................................... 593 KBCRH .............................................. 594 KBCRL............................................... 596 KBTR ................................................. 598 LADR ................................................. 634 LPWRCR............................................ 844 MDCR .............................................
Shift instructions....................................... 50 Single mode ............................................ 735 Sleep mode ............................................. 851 Smart card............................................... 403 Smart card interface................................ 449 Software protection................................. 799 Software standby mode........................... 851 Stack pointer (SP) ..................................... 38 Stack status ...........................
Rev. 2.00 Sep.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2117R Group Publication Date: Rev.1.00, April 28, 2008 Rev.2.00, September 28, 2009 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2009. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2117R Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0452-0200