Datasheet

Section 28 Electrical Characteristics
Rev. 2.00 Sep. 28, 2009 Page 972 of 994
REJ09B0452-0200
φ
t
TDPCKS
TDPCKI
t
TDPCKW
t
TDPCKW
Figure 28.18 TDP Clock Input Timing
φ
PWMU5A to PWMU0A,
PWMU5B to PWMU0B,
PWX1, PWX0
t
PWOD
Figure 28.19 PWMU, PWMX Output Timing
t
Scyc
t
SCKr
t
SCKW
SCK1
t
SCKf
Figure 28.20 SCK Clock Input Timing
SCK1
TxD1
(transmit data)
RxD1
(receive data)
t
TXD
t
RXH
t
RXS
Figure 28.21 SCI Input/Output Timing (Clock Synchronous Mode)