Datasheet

Section 7 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 191 of 994
REJ09B0452-0200
Port
Output
Specification
Signal Name
Output
Signal
Name
Signal Selection
Register Settings
Internal Module Settings
7 RTS_OE RTS LPC.HICR5.SCIFE, SCIFCR.SCIFOE1,
SCIFOE0
SCIFOE = 1: (SCIFE • SCIFOE1 • SCIFOE0 +
SCIFE • SCIFOE0)
FSISS_OE FSISS FSI.FSICR1.FSIE = 1
6 FSICK_OE FSICK FSI.FSICR1.FSIE = 1
5 DTR_OE DTR LPC.HICR5.SCIFE, SCIFCR.SCIFOE1,
SCIFOE0
SCIFOE=1: (SCIFE • SCIFOE1 • SCIFOE0 +
SCIFE • SCIFOE0)
4 FSIDO_OE FSIDO FSI.FSICR1.FSIE = 1
3 PWMU1B_OE PWMU1B PWMU_B.PWMCONB.PWM1E = 1
2 PWMU0B_OE PWMU0B PWMU_B.PWMCONB.PWM0E = 1,
PWMU_B.PWMCONC.CNTMD01 = 0
1 LSCI_OE LSCI LPC.HICR0.LSCIE = 1
PB
0 LSMI_OE LSMI LPC.HICR0.LSMIE = 1
7 TIOCB2_OE TIOCB2 TPU.TIOR2.IOB3 = 0,
TPU.TIOR2.IOB[1:0] = 01/10/11
6 TIOCA2_OE TIOCA2 TPU.TIOR2.IOA3 = 0,
TPU.TIOR2.IOA[1:0] = 01/10/11
5 TIOCB1_OE TIOCB1 TPU.TIOR1.IOB3 = 0,
TPU.TIOR1.IOB[1:0] = 01/10/11
4 TIOCA1_OE TIOCA1 TPU.TIOR1.IOA3 = 0,
TPU.TIOR1.IOA[1:0] = 01/10/11
3 TIOCD0_OE TIOCD0 TPU.TIOR0.IOD3 = 0,
TPU.TIOR0.IOD[1:0] = 01/10/11
2 TIOCC0_OE TIOCC0 TPU.TIOR0.IOC3 = 0,
TPU.TIOR0.IOC[1:0] = 01/10/11
PC
1 TIOCB0_OE TIOCB0 TPU.TIOR0.IOB3 = 0,
TPU.TIOR0.IOB[1:0] = 01/10/11
0 TIOCA0_OE TIOCA0 TPU.TIOR0.IOA3 = 0,
TPU.TIOR0.IOA[1:0] = 01/10/11