Datasheet

Section 9 14-Bit PWM Timer (PWMX)
Rev. 2.00 Sep. 28, 2009 Page 227 of 994
REJ09B0452-0200
Table 9.4 Reading/Writing to 16-bit Registers
Read Write
Register Word Byte Word Byte
DADRA, DADRB O O O ×
DACNT O × O ×
[Legend]
O: Enabled access.
Word-unit access includes accessing byte sequentially, first upper byte, and then lower
byte.
×: The result of the access in the unit cannot be guaranteed.
(a) Write to upper byte
CPU
[H'AA]
Upper byte
TEMP
[H'AA]
DACNTH
[ ]
DACNTL
[ ]
Bus interface
Module data bus
(b) Write to lower byte
CPU
[H'57]
Lower byte
TEMP
[H'AA]
DACNTH
[H'AA]
DACNTL
[H'57]
Bus interface
Module data bus
Figure 9.2 DACNT Access Operation (1) [CPU → DACNT (H'AA57) Writing]