Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Sep. 28, 2009 Page 278 of 994
REJ09B0452-0200
(b) When TGR is an input capture register
Figure 10.20 shows an operation example in which TGRA has been designated as an input capture
register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by
TGRA input capture has been set for TCNT, and both rising and falling edges have been selected
as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT
value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA
is simultaneously transferred to TGRC.
TCNT value
H'09FB
H'0000
TGRC
Time
H'0532
TIOCA
TGRA
H'0F07H'0532
H'0F07
H'0532
H'0F07
H'09FB
Figure 10.20 Example of Buffer Operation (2)