Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Sep. 28, 2009 Page 299 of 994
REJ09B0452-0200
10.8.5 Conflict between TGR Write and Compare Match
If a compare match occurs in the T
2
state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is inhibited. A compare match does not occur even if the same value
as before is written. Figure 10.46 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T1
T2
NM
TGR write data
TGR
N N+1
Prohibited
Figure 10.46 Conflict between TGR Write and Compare Match