Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Sep. 28, 2009 Page 303 of 994
REJ09B0452-0200
10.8.10 Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence. Figure 10.51 shows the operation timing when a
TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Counter
clear signal
TCNT input
clock
φ
TCNT
TGF
Disabled
TCFV
H'FFFF H'0000
Figure 10.51 Conflict between Overflow and Counter Clearing