Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxxvii of xl
REJ09B0452-0200
21.3.6 FSI Program Instruction Register (FSIPPINS) ..................................................... 691
21.3.7 FSI Status Register (FSISTR) ............................................................................... 691
21.3.8 FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7)............................... 693
21.3.9 FSI Receive Data Register (FSIRDR)................................................................... 693
21.3.10 FSI Access Host Base Address Registers H and L
(FSIHBARH and FSIHBARL) ............................................................................. 694
21.3.11 FSI Flash Memory Size Register (FSISR)............................................................ 694
21.3.12 FSI Command Host Base Address Registers H and L
(CMDHBARH and CMDHBARL) ...................................................................... 695
21.3.13 FSI Command Register (FSICMDR).................................................................... 696
21.3.14 FSI LPC Command Status Register 1 (FSILSTR1).............................................. 696
21.3.15 FSI LPC Command Status Register 2 (FSILSTR2).............................................. 698
21.3.16 FSI General-Purpose Registers 1 to F (FSIGPR1 to FSIGPRF) ........................... 699
21.3.17 FSI LPC Control Register (SLCR) ....................................................................... 699
21.3.18 FSI Address Registers H, M, and L (FSIARH, FSIARM, and FSIARL) ............. 700
21.3.19 FSI Write Data Registers HH, HL, LH, and LL
(FSIWDRHH, FSIWDRHL, FSIWDRLH, and FSIWDRLL).............................. 701
21.4 Operation ........................................................................................................................... 703
21.4.1 LPC/FW Memory Cycles ..................................................................................... 703
21.4.2 SPI Flash Memory Transfer.................................................................................. 705
21.4.3 Flash Memory Instructions ................................................................................... 706
21.4.4 FSI Memory Cycle (Direct Transfer between LPC and SPI)................................ 707
21.4.5 FSI Memory Cycle (LPC-SPI Command Transfer).............................................. 714
21.4.6 SPI Flash Memory Write Operation Mode ........................................................... 722
21.5 Reset Conditions ................................................................................................................ 723
21.6 Interrupt Sources................................................................................................................ 725
21.7 Usage Note......................................................................................................................... 725
21.7.1 Longword Transfer in FW Memory Write Cycles................................................ 725
Section 22 A/D Converter....................................................................................727
22.1 Features .............................................................................................................................. 727
22.2 Input/Output Pins ............................................................................................................... 729
22.3 Register Descriptions ......................................................................................................... 730
22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 731
22.3.2 A/D Control/Status Register (ADCSR) ................................................................ 732
22.3.3 A/D Control Register (ADCR) ............................................................................. 734
22.4 Operation ........................................................................................................................... 735
22.4.1 Single Mode.......................................................................................................... 735
22.4.2 Scan Mode ............................................................................................................ 736
22.4.3 Input Sampling and A/D Conversion Time .......................................................... 737