Datasheet

Section 12 16-Bit Duty Period Measurement Timer (TDP)
Rev. 2.00 Sep. 28, 2009 Page 351 of 994
REJ09B0452-0200
12.6 Usage Notes
12.6.1 Conflict between TDPCNT Write and Count-Up Operation
If a conflict between a TDPCNT write and counting up operation occurs in the second half of the
TDPCNT write cycle, writing to TDPCNT takes precedence and TDPCNT is not incremented.
Figure 12.13 shows the timing of this conflict.
φ
Internal write
signal
Write data M
Internal clock
TDPCNT
input clock
T1
T2
TDPCNT N - 1 M M + 1
Figure 12.13 Conflict between TDPCNT Write and Counting Up
12.6.2 Conflict between TDPPDMX Write and Compare Match
If a conflict between a TDPPDMX write and a compare match occurs in the second half of the
TDPPDMX write cycle, writing to TDPPDMX takes precedence and the compare match signal is
inhibited. Figure 12.14 shows the timing of this conflict.
φ
Internal write
signal
TDPCNT
TDPPDMX
T1
T2
Compare
match signal
Inhibited
N N + 1
N+ 2
N
M
Figure 12.14 Conflict between TDPPDMX Write and Compare Match