Datasheet

Section 15 Serial Communication Interface (SCI)
Rev. 2.00 Sep. 28, 2009 Page 454 of 994
REJ09B0452-0200
3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this
case, one frame of data is determined to have been transmitted including re-transfer, and the
TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is
set to 1. Writing transmit data to TDR starts transmission of the next data.
Figure 15.28 shows a sample flowchart for transmission. In transmission, the TEND and TDRE
flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request when TIE in SCR
is set. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission,
TEND remains 0. Therefore, the SCI automatically transmit the specified number of bytes,
including re-transmission in the case of error. However, the ERS flag is not automatically cleared;
the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt
request to be generated at error occurrence.
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4Ds
(n + 1) th
transfer frame
Retransfer frame
nth transfer frame
TDRE
TEND
[1]
FER/ERS
Transfer from TDR to TSR Transfer from TDR to TSR Transfer from TDR to TSR
[2] [3]
[3]
Figure 15.26 Data Re-transfer Operation in SCI Transmission Mode
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR,
which is shown in figure 15.27.
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp I/O data
12.5 etu
TXI
(TEND interrupt)
11.0 etu
DE
Guard time
GM = 0
GM = 1
[Legend]
Ds: Start bit
D0 to D7: Data bits
Dp: Parity bit
DE: Error signal
etu: Element Time Unit (time taken to transfer one bit)
Figure 15.27 TEND Flag Set Timings during Transmission