Datasheet

Section 16 CIR Interface
Rev. 2.00 Sep. 28, 2009 Page 471 of 994
REJ09B0452-0200
16.2 Input Pins
Table 16.1 shows the input pin of the CIR.
Table 16.1 Pin Configuration
Pin Name Symbol I/O Function
CIR input pin CIRI Input CIR receive data input pin
16.3 Register Description
Table 16.2 shows the CIR register configuration.
Table 16.2 List of Register Addresses
Register Name Abbreviation R/W Initial Value Address
Receive control register 1 CCR1 R/W H'00 H'FA40
Receive control register 2 CCR2 R/W H'00 H'FA41
Receive status register CSTR R/W H'00 H'FA42
Interrupt enable register CEIR R/W H'00 H'FA43
Bit rate register BRR R/W H'FF H'FA44
Receive data register 0 to 17 CIRRDR0 to
CIRRDR17
R H'00 H'FA45
Header minimum high-level period register HHMIN R/W H'0000 H'FA46
Header maximum high-level period register HHMAX R/W H'0000 H'FA48
Header minimum low-level period register HLMIN R/W H'00 H'FA4A
Header maximum low-level period register HLMAX R/W H'00 H'FA4B
Data level 0 minimum period register DT0MIN R/W H'00 H'FA4C
Data level 0 maximum period register DT0MAX R/W H'00 H'FA4D
Data level 1 minimum period register DT1MIN R/W H'00 H'FA4E
Data level 1 maximum period register DT1MAX R/W H'00 H'FA4F