Datasheet

Section 16 CIR Interface
Rev. 2.00 Sep. 28, 2009 Page 476 of 994
REJ09B0452-0200
16.3.4 Interrupt Enable Register (CEIR)
CEIR consists of the bits that enable/disable various interrupts.
Bit Bit Name
Initial
Value
R/W Description
7, 6 ⎯ All 0 R/W Reserved
The initial value should not be changed.
5 REPIE 0 R/W Repeat Detection Interrupt Enable
0: REPI interrupt request is disabled.
1: REPI interrupt request is enabled.
4 OVEIE 0 R/W Overrun Error Interrupt Enable
0: OVEI interrupt request is disabled.
1: OVEI interrupt request is enabled.
3 RENDIE 0 R/W Receive End Interrupt Enable
0: RENDI interrupt request is disabled.
1: RENDI interrupt request is enabled.
2 ABIE 0 R/W Abort Interrupt Enable
0: ABI interrupt request is disabled.
1: ABI interrupt request is enabled.
1 FREIE 0 R/W Framing Error Interrupt Enable
0: FREI interrupt request is disabled.
1: FREI interrupt request is enabled.
0 HEADFIE 0 R/W Header Detection Interrupt Enable
0: HEADFI interrupt request is disabled.
1: HEADFI interrupt request is enabled.