Datasheet

Section 16 CIR Interface
Rev. 2.00 Sep. 28, 2009 Page 485 of 994
REJ09B0452-0200
Table 16.4 An Example of Signal Type Determination Register Setting
Description
Register
Name
Symbol
Setting
Value
Setting
Time
Prescribed
Time
(Error: 30%) Notes
Minimum high-level period
for a header or repeat
header and minimum low-
level period for a stop
HHMIN A H'079 6.34 ms 6.3 ms HHMIN9 to
HHMIN0
Maximum high-level period
for a header or repeat
header and maximum low-
level period for a stop
HHMAX A H'0DF 11.7 ms 11.7 ms HHMAX9 to
HHMAX0
Minimum low-level period
for a header
HLMIN B H'3D 3.20 ms 3.15 ms
Maximum low-level period
for a header
HLMAX B H'6F 5.82 ms 5.85 ms
Minimum value of low/high-
level period for logic 0, high-
level period for logic 1, and
high-level period for a burst
DT0MIN C H'07 0.37 ms 0.39 ms
Maximum value of low/high-
level period for logic 0, high-
level period for logic 1, and
high-level period for a burst
DT0MAX C H'0D 0.68 ms 0.73 ms
Minimum low-level period
for logic 1
DT1MIN D H'0F 0.78 ms 0.78 ms
Maximum low-level period
for logic 1
DT1MAX D H'1B 1.42 ms 1.46 ms
Minimum low-level period
for a repeat header
RMIN E H'1F 1.62 ms 1.58 ms
Maximum low-level period
for a repeat header
RMAX E H'37 2.88 ms 2.92 ms
Note: The above table shows the values when the system clock is 10MHz, CLK1, CLK0 = B'10,
and BRR = H'82 (when the error is 30%).