Datasheet

Section 16 CIR Interface
Rev. 2.00 Sep. 28, 2009 Page 488 of 994
REJ09B0452-0200
16.5 Noise Canceler Circuit
The CIR incorporates a 4-stage noise canceler. The FLTE, FLT, and FLTCK1 and FLTCK0 bits
in HHMAX enable/disable the noise canceler circuit, select the number of stages of the noise
canceler circuit, and select the division ratio for generating the noise canceler circuit clock,
respectively. Figure 16.6 shows a block diagram of the noise canceler circuit.
CIRI
FLTE = 0
F. F
F. F F. F F. F
F. F
F. F
F. F
F. F
CIR DATA
Noise canceler circuit
FLTCK1, FLTCK0
Clock generation circuit for noise canceler circuit
CIR sampling clock
Sampling clock generation circuit
φ
φ/2
φ/4
φsub
Figure 16.8 Noise Canceler Circuit