Datasheet

Section 16 CIR Interface
Rev. 2.00 Sep. 28, 2009 Page 489 of 994
REJ09B0452-0200
Table 16.5 shows sample settings for the noise canceler circuit.
Table 16.5 Sample Settings for Noise Canceler Circuit
φ
CLK1 and
CLK0
Setting
BRR
Setting
FLTCK1 and
FLTCK0
Setting
CIR
Sampling
Clock
Number of Stages
of Noise Canceler
Circuit
Width of
Noise
Cancellation
10 MHz φ H'80 Not divided 12.9 μs 0 12.9 μs
1 25.8 μs
2 38.7 μs
3 51.6 μs
4 64.5 μs
Divided by 2 25.8 μs 0 25.8 μs
2 77.4 μs
4 129 μs
Divided by 4 51.6 μs 0 51.6 μs
2 154.8 μs
4 258 μs
Divided by 8 103.2 μs 0 103.2 μs
2 309.6 μs
4 516 μs
⎯ φsub H'00 Not divided 31.3 μs 0 31.3 μs
1 62.5 μs
2 93.8 μs
3 125 μs
4 156 μs
Divided by 2 62.5 μs 0 62.5 μs
2 187.5 μs
4 312.5 μs
Divided by 4 125 μs 0 125 μs
2 375 μs
4 625 μs
Divided by 8 250 μs 0 250 μs
2 750 μs
4 1.25 ms