Datasheet

Section 16 CIR Interface
Rev. 2.00 Sep. 28, 2009 Page 490 of 994
REJ09B0452-0200
16.6 Reset Conditions
The range of initialization caused by a system reset, a software reset controlled by the SRES bit in
CCR1, or an abort is shown in table 16.6.
Table 16.6 Range of Initialization of CIR
HHMIN, HHMAX,
HLMIN, HLMAX,
DT0MIN, DT0MAX,
DT1MIN, DT1MAX,
CCR1, CCR2,
CEIR
RFMBN bit
in HHMIN CIRRDR CSTR
Sequence
Block BRR
System reset Initialized Initialized Initialized Initialized Initialized Initialized
SRES software
reset
Retained Initialized Initialized Initialized Initialized Initialized
Abort Retained Retained Retained Retained *
(CIRBUSY
is initialized.)
Initialized Retained
16.7 Interrupt Sources
The CIR has six interrupt source flags for this LSI. Setting the corresponding enable bit to 1
enables the relevant interrupt request to be issued. Since the six interrupt requests are allocated to
one vector address, it is necessary for the CPU to check the interrupt request flags in order to
determine which interrupt source has caused the interrupt to be requested.
Table 16.7 Interrupt Sources
Interrupt Name Interrupt Source Flags Interrupt Enable Bit
RENDI REND Receive end RENDIE
OVEI OVRF Overrun error OVEIE
REPI REPF Repeat detection REPIE
FREI FRF Framing error FREIE
ABI ABF Abort ABIE
HEADFI HEADF Header detection HEADFIE