Datasheet

Section 17 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 28, 2009 Page 496 of 994
REJ09B0452-0200
17.3 Register Descriptions
The SCIF has the following registers. The register configuration of the SCIF is shown below.
Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in MSTPCRB. For details,
see table 17.3. For the SCIF address registers H and L (SCIFADRH, SCIFADRL) and serial IRQ
control register 4 (SIRQCR4), see section 20, LPC Interface (LPC).
Table 17.2 Register Configuration
Register Name Abbreviation R/W Initial Value Address
Data
Bus
Width
Host interface control register 5 HICR5 R/W H'00 H'FFFE33 8
Module stop control register B MSTPCRB R/W H'00 H'FFFE7F 8
Receive buffer register FRBR R H'00
Transmitter holding register FTHR W ⎯
Divisor latch L FDLL R/W H'00
H'FFFC20 8
Interrupt enable register FIER R/W H'00
Divisor latch H FDLH R/W H'00
H'FFFC21 8
Interrupt identification register FIIR R H'01
FIFO control register FFCR W H'00
H'FFFC22 8
Line control register FLCR R/W H'00 H'FFFC23 8
Modem control register FMCR R/W H'00 H'FFFC24 8
Line status register FLSR R H'60 H'FFFC25 8
Modem status register FMSR R ⎯ H'FFFC26 8
Scratch pad register FSCR R/W H'00 H'FFFC27 8
SCIF control register SCIFCR R/W H'00 H'FFFC28 8
SCIF address register H SCIFADRH R/W H'03 H'FFFDC4 8
SCIF address register L SCIFADRL R/W H'F8 H'FFFDC5 8
Serial IRQ control register 4 SIRQCR4 R/W H'00 H'FFFE3B 8