Datasheet

Section 17 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 28, 2009 Page 528 of 994
REJ09B0452-0200
17.5 Interrupt Sources
Table 17.9 lists the interrupt sources. A common interrupt vector is assigned to each interrupt
source.
When the LPC uses the SCIF, the LPC does not request any interrupts to be sent to the H8S CPU.
The SERIRQ signal of the LPC interface transmits an interrupt request to the host.
Table 17.9 Interrupt Sources
Interrupt Name Interrupt Source Priority
Receive line status Overrun error, parity error, framing error, break interrupt High
Receive data ready Acceptance of receive data, FIFO trigger level
Character timeout
(when FIFO is enabled)
No data is input to or output from the receive FIFO for the 4-
character time period while one or more characters remain in
the receive FIFO.
FTHR empty FTHR empty
Modem status CTS, DSR, RI, DCD Low
Table 17.10 shows the interrupt source, vector address, and interrupt priority.
Table 17.10 Interrupt Source, Vector Address, and Interrupt Priority
Interrupt
Origin of Interrupt Source Interrupt Name
Vector
Number
Vector
Address ICR
SCIF SCIF (SCIF interrupt) 82 H'000148 ICRC7
17.6 Usage Note
17.6.1 Power-Down Mode When LCLK Is Selected for SCLK
To switch to watch mode or software standby mode when LCLK divided by 18 has been selected
for SCLK, use the shutdown function of the LPC interface to stop LCLK.
17.6.2 FLCR Access During Serial Transmission and Reception
Set FLCR to its initial value and do not write to it during serial transmission or reception.