Datasheet

Section 18 I
2
C Bus Interface (IIC)
Rev. 2.00 Sep. 28, 2009 Page 530 of 994
REJ09B0452-0200
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (SCL/SDA pin)
⎯ Ten pins—P52/SCL0, P97/SDA0, P86/SCL1, P42/SDA1, PG2/SDA2, PG3/SCL2,
PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB —(normally NMOS
push-pull outputs) function as NMOS open-drain outputs when the bus drive function is
selected.
Note: When using this IIC module, make sure to set bits HNDS, FNC1, and FNC0 in ICXR to 1
in the initial settings. If other settings are made, restrictions on operation that are not
covered in this manual will apply.
Figure 18.1 shows a block diagram of the I
2
C bus interface. Figure 18.2 shows an example of I/O
pin connections to external circuits. Since I
2
C bus interface I/O pins are different in structure from
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 28, Electrical Characteristics.