Datasheet

Section 20 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 635 of 994
REJ09B0452-0200
When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of
LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded
as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4
in LADR3 is inverted, and the values of bits 3 to 0 are ignored.
• Host select register
I/O Address
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Transfer
Cycle Host Select Register
Bit 4 Bit 3 0 Bit 1 0 I/O write IDR3 write, C/D3 ← 0
Bit 4 Bit 3 1 Bit 1 0 I/O write IDR3 write, C/D3 ← 1
Bit 4 Bit 3 0 Bit 1 0 I/O read ODR3 read
Bit 4 Bit 3 1 Bit 1 0 I/O read STR3 read
Bit 4 0 0 0 0 I/O write TWR0MW write
0 0 0 1
: : : :
Bit 4
1 1 1 1
I/O write TWR1 to TWR15 write
Bit 4 0 0 0 0 I/O read TWR0SW read
0 0 0 1 I/O read Bit 4
: : : :
TWR1 to TWR15 read
1 1 1 1
Note: * When channel 3 is used, the content of LADR3 must be set so that the addresses for
channels 1, 2, 4, and SCIF are different.