Datasheet

Section 2 CPU
Rev. 2.00 Sep. 28, 2009 Page 30 of 994
REJ09B0452-0200
⎯ 16 ÷ 8-bit register-register divide: 12 states
⎯ 16 × 16-bit register-register multiply: 3 states
⎯ 32 ÷ 16-bit register-register divide: 20 states
• Two CPU operating modes
⎯ Normal mode*
⎯ Advanced mode
• Power-down state
⎯ Transition to power-down state by the SLEEP instruction
⎯ CPU clock speed selection
Note: * Normal mode is not available in this LSI.
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported by the H8S/2600 CPU only.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600
CPU only.
• The number of execution states of the MULXU and MULXS instructions;
Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MULXU.B Rs, Rd 2* 12 MULXU
MULXU.W Rs, ERd 2* 20
MULXS.B Rs, Rd 3* 13 MULXS
MULXS.W Rs, ERd 3* 21
CLRMAC CLRMAC 1*
LDMAC ERs,MACH 1* LDMAC
LDMAC ERs,MACL 1*
STMAC STMAC MACH,ERd 1*
Not supported
STMAC MACl,ERd 1*
Note: * This becomes one state greater immediately after a MAC instruction.
In addition, there are differences in address space, CCR and EXR register functions,
and power-down modes, etc., depending on the model.