Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 688 of 994
REJ09B0452-0200
21.3.2 FSI Control Register 2 (FSICR2)
The FSICR2 control bits are classified into two functionalities: enabling/disabling the FSI
communications and enabling/disabling the FSI internal interrupts.
R/W
Bit Bit Name
Initial
Value EC Host Description
7 TE 0 R/W ⎯ FSI Transmit Enable
Controls FSI transmission and indicates transmission
status in combination with the LFBUSY bit.
0: FSI transmission wait state
[Clearing condition]
When FSI data transmission is completed.
1: When LFBUSY = 0: Starts transmission.
When LFBUSY = 1: FSI transmission is in progress
(automatically set).
6 RE 0 R/W ⎯ FSI Reception Enable
Controls FSI reception and indicates reception status
in combination with the LFBUSY bit.
0: FSI reception wait state
[Clearing condition]
When FSI data reception is completed.
1: When LFBUSY = 0: Starts reception.
When LFBUSY = 1: FSI reception is in progress
(automatically set).
5 FSITEIE 0 R/W ⎯ FSI Transmit End Interrupt Enable
0: Disables the FSITEI interrupt request.
1: Enables the FSITEI interrupt request.
4 FSIRXIE 0 R/W ⎯ FSI Receive Interrupt Enable
0: Disables the FSIRXI interrupt request.
1: Enables the FSIRXI interrupt request.
3 to 0 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be modified.