Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 692 of 994
REJ09B0452-0200
R/W
Bit Bit Name
Initial
Value
EC Host Description
6 OBF 0 R ⎯ Transmit Data Register Full
Indicates whether or not there is data to be written by
the EC (this LSI).
0: There is no write data.
[Clearing condition]
When write data transmission to the SPI flash memory
is completed.
1: There is write data.
[Setting condition]
When the TE bit is set to 1.
5 FSIRXI 0 R ⎯ FSI Receive End Interrupt Flag
Indicates whether or not there is data to be read by
the EC (this LSI).
0: There is no read data.
[Clearing condition]
• LFBUSY = 0: When all receive data has been read
by the EC (when RBN is cleared to 0).
• LFBUSY = 1: When all receive data has been I/O-
read by the host (automatically cleared).
1: There is read data.
[Setting condition]
When receive data has been transferred to FSIRDR.
4 to 0 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be modified.
Note: * Only 0 can be written to bit 7 to clear it.