Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 695 of 994
REJ09B0452-0200
R/W
Bit Bit Name
Initial
Value
EC Host Description
7 to 2 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be changed.
1
0
FSIMS1
FSIMS0
0
0
R/W
R/W
⎯
⎯
These bits specify the SPI flash memory size.
00: 1 MB
01: 2 MB
10: 4 MB
11: 8 MB
21.3.12 FSI Command Host Base Address Registers H and L (CMDHBARH and
CMDHBARL)
CMDHBARH and CMDHBARL set the upper 16 bits of the host start address which is necessary
to set a command address. The lower 16 bits of the host start address range from H'F000 to
H'F00F. If a host address to be input to CMDHBARH and CMDHBARL is out of the determined
range, Sync will not be returned. If FW memory cycle is used, bit 31 to bit 28 in CMDHBARH is
set as IDSEL. During FSI operation (in the state where FSIE or FSILIE is set), do not change the
setting in this register.
• CMDHBARH
R/W
Bit Bit Name
Initial
Value EC Host Description
7 to 0 bit 31 to
bit 24
All 0 R/W ⎯ These bits specify bits [31:24] of the host start
address.
• CMDHBARL
R/W
Bit Bit Name
Initial
Value EC Host Description
7 to 0 bit 23 to
bit 16
All 0 R/W ⎯ These bits specify bits [23:16] of the host start
address.