Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 698 of 994
REJ09B0452-0200
21.3.15 FSI LPC Command Status Register 2 (FSILSTR2)
FSILSTR2 indicates the LPC internal status.
R/W
Bit Bit Name
Initial
Value
EC Host Description
7 to 5 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be modified.
4 FSIDWBUSY 0 R ⎯ FSI Direct Write Busy Flag
Indicates a FSI write transfer status during LPC-
SPI direct transfer.
0: FSI write transfer is completed.
1: During FSI write transfer
3 FSIDRBUSY 0 R ⎯ FSI Direct Read Busy Flag
Indicates a FSI read transfer status during LPC-
SPI direct transfer.
0: FSI read transfer is completed.
1: During FSI read transfer
2 to 0 SIZE2
SIZE1
SIZE0
0
0
1
R
R
R
⎯
⎯
⎯
Transfer Byte Count Monitor
Indicates the number of transferred bytes when
data is received in the LPC/FW memory cycles.
When the Byte/Page-Program or AAI-Program
instruction is executed from the EC CPU, the
number of transferred bytes can be confirmed by
these bits.
001: LPC/FW memory cycle (byte transfer)
010: FW memory cycle (word transfer)
100: FW memory cycle transfer (longword
transfer)
When a transfer is made in units other than
byte/word/longword, the previous value is
retained.
Note: This bit is not set to the value other than
above.