Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 712 of 994
REJ09B0452-0200
Internal register
First receive data
Second receive data
Third receive data
Fourth receive data
H'01
H'23
H'45
H'67
H'70
H'4A
H'06
H'03
FSIRDR3
FSIRDR0
FSITDR3
FSITDR0
FSIAR[7:0]
FSIAR[15:8]
FSIAR[23:16]
H'67_45_23_01
H'06_4A_70
H'03
FSIAR[23:0]
FSIRDINS[7:0]
FSISFR
FSIDI
FSIDO
Figure 21.8 Data Transfer to FSIRDR (Example)
LCLK
LFRAME
LAD[3:0]
ST CT ADDR DATATA R WA IT S Y TA R
φ
FSIAR[23:0]
FSIRDINS[7:0]
FSICR2 RE bit
FSITDR7 to
FSITDR0
FSISTR FSIRXI bit
FSISS
FSICK (CPOS = CPHS =0)
FSIDO
H'06-4A-70
H'70-4A-06-03
H'02->06->4A->70
H'01->23->45->67
H'01->23->45->67
H'03
FSIRDR3 to
FSIRDR0
FSIDI
Figure 21.9 Read Instruction Execution Timing