Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 716 of 994
REJ09B0452-0200
(3) FSI Command Read
Figure 21.13 shows an example of FSI command read.
CMDHBAR: H'EFFF
H'EFFF_0000
∗
H'EFFF_F000
H'EFFF_F00F
H'EFFF_FFFF
CMD0
CMD1
CMDE
CMDF
FSILSTR1
FSIGPR1
FSIGPRE
FSIGPRF
FSIGPR2 to D
Host address
Note:
*
The upper 16 bits of the host address are set to the value in the CMDHBAR register.
LPC internal flags
EC CPU write
Figure 21.13 FSI Command Read (Example)
As shown in figure 21.13, if a host address ranging from H'EFFF_F000 to H'EFFF_F00F is
accessed in LPC/FW memory read cycle while the CMDHBAR register is set to H'EFFF, the
FSILSTR1 or data in FSIGPR1 to FSIGPRF is returned. Sync is not returned if the host address to
be input is out of the determined range. In FSI command read, no wait cycle will be inserted to the
LPC bus cycle. Before reading the FSIGPR, ensure that the CMDBUSY bit in FSILSTR1 has
been cleared to 0.