Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 725 of 994
REJ09B0452-0200
21.6 Interrupt Sources
The FSI has four interrupt sources for the slave (this LSI): FSITEI, FSIRXI, FSICMDI, and
FSIWI. FSITEI is a transmit end interrupt when the slave executes the SPI flash memory write
transfer. FSIRXI is a receive end interrupt when the slave executes the SPI flash memory read
transfer. FSICMDI is a command receive interrupt in host FSI command write. FSIWI is a write
receive interrupt in the case of write from the host to the SPI flash memory. Setting the
corresponding enable bit to 1 enables the relevant interrupt request to be issued.
Table 21.9 FSI Interrupt Sources
Interrupt Name Interrupt Source Interrupt Enable Bit
FSII FSITEI Transmit end FSITEIE
FSIRXI Receive data full FSIRXIE
LFSII FSICMDI FSI command reception FSICMDIE
FSIWI FSI write reception FSIWIE
21.7 Usage Note
21.7.1 Longword Transfer in FW Memory Write Cycles
When longword transfers of FW memory write cycles are used, the maximum operating frequency
of the system clock is 10 MHz.