Datasheet

Section 3 MCU Operating Modes
Rev. 3.00 Sep. 28, 2009 Page 69 of 910
REJ09B0350-0300
3.2.2 System Control Register (SYSCR)
SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for
NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables
the on-chip RAM address space.
Bit Bit Name
Initial
Value
R/W Description
7, 6 — All 0 R Reserved
The initial value should not be changed.
5
4
INTM1
INTM0
0
0
R
R/W
Interrupt Control Select Mode 1 and 0
These bits select the interrupt control mode of the
interrupt controller.
For details on the interrupt control modes, see section
5.6, Interrupt Control Modes and Interrupt Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
3 XRST 1 R External Reset
Indicates the reset source. A reset is caused by an
external reset input, or when the watchdog timer
overflows.
0: A reset is caused when the watchdog timer overflows
1: A reset is caused by an external reset
2 NMIEG 0 R/W NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input