Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 105 of 910
REJ09B0350-0300
• WER
Bit Bit Name Initial Value R/W Description
7 WUEE 0 R/W WUE Enable
The WUE interrupt request is enabled when this bit|
is 1.
0: Wake-up input interrupt request is disabled
1: Wake-up input interrupt request is enabled
6 to 0 ⎯ All 0 R/W Reserved
The initial values should not be changed.
5.4 Interrupt Sources
5.4.1 External Interrupt Sources
The interrupt sources of external interrupts are NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15
to WUE8. These interrupts can be used to restore this LSI from software standby mode.
(1) NMI Interrupt
The nonmaskable external interrupt NMI is the highest-priority interrupt, and is always accepted
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or falling
edge on the NMI pin.
(2) IRQ15 to IRQ0 Interrupts:
Interrupts IRQ15 to IRQ0 are requested by an input signal at pins IRQ15 to IRQ0 or pins
ExIRQ15 to ExIRQ6. Interrupts IRQ15 to IRQ0 have the following features:
• The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an
independent vector address.
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ6.
• Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.
• The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to
0 by software.