Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 128 of 910
REJ09B0350-0300
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
H'0310
φ
Address bus
Break request
signal
Breakpoint NOP instruction is executed at breakpoint address H'0312 and
next address, H'0314; fetch from address H'0316 starts after
end of exception handling.
Breakpoint NOP instruction at breakpoint address H'0312 is not executed;
fetch from address H'0312 starts after end of exception handling.
Breakpoint MOV instruction is executed at breakpoint address H'0312,
NOP instruction at next address, H'0316, is not executed;
fetch from address H'0316 starts after end of exception handling.
H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036
H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036
H'0310 H'0312 H'0314 SP-2 SP-4
H'0036
H'0310 NOP
H'0312 MOV.W #xx : 16,Rd
H'0314 NOP
H'0316 NOP
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
• Program area in on-chip memory, 1-state execution instruction at specified break address
φ
Address bus
Break request
signal
• Program area in on-chip memory, 2-state execution instruction at specified break address
φ
Address bus
Break request
signal
• Program area in external memory (2-state access, 16-bit-bus access), 1-state execution instruction
at specified break address (Not available in this LSI)
Instruction
fetch
NOP
execution
NOP
execution
MOV.W
execution
NOP
execution
NOP
execution
Interrupt exeption handling
Interrupt exeption handling
NOP
execution
Interrupt exeption handling
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Vector
fetch
Internal
operation
Stack save
Internal
operation
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Vector
fetch
Internal
operation
Internal
operation
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Vector
fetch
Internal
operation
Stack save
Stack save
Internal
operation
Figure 5.12 Examples of Address Break Timing