Datasheet

Section 7 I/O Ports
Rev. 3.00 Sep. 28, 2009 Page 187 of 910
REJ09B0350-0300
Table 7.4 Available Output Signals and Settings in Each Port
Port
Output
Specification
Signal Name
Output
Signal
Name
Signal Selection
Register Settings
Internal Module Settings
7 P17_OE P17
6 P16_OE P16
5 P15_OE P15
4 P14_OE P14
3 P13_OE P13
2 P12_OE P12
1 P11_OE P11
P1
0 P10_OE P10
7 P27_OE P27
6 P26_OE P26
5 P25_OE P25
4 P24_OE P24
3 P23_OE P23
2 P22_OE P22
1 P21_OE P21
P2
0 P20_OE P20
7 SERIRQ_OE SERIRQ
6 P36_OE P36
5 P35_OE P35
4 P34_OE P34
3 LAD3_OE LAD3
2 LAD2_OE LAD2
P3
1 LAD1_OE LAD1
LPC.HICR5.SCIFE, HICR4.LPC4E,
HICR0.LPC[3E:1E]
LPCENABLE = 1: SCIFE+LPC4E + LPC3E +
LPC2E + LPC1E
0 LAD0_OE LAD0