Datasheet

Section 8 8-Bit PWM Timer (PWMU)
Rev. 3.00 Sep. 28, 2009 Page 208 of 910
REJ09B0350-0300
(2) 16-Bit Single Pulse Mode
When 16-bit single pulse mode is selected, PWMPRE0, PWMPRE2, and PWMPRE4 are valid.
The settings of PWMPRE1, PWMPRE3, and PWMPRE5 are invalid.
PWM cycle = [65535 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255)
Table 8.4 Resolution, PWM Conversion Period, and Carrier Frequency (16-Bit Counter
Operation) when φ = 20 MHz
Carrier Frequency
PWM Conversion Period Single Pulse Mode
Internal Clock
Frequency
Resolution Min. Max. Min. Max.
φ 50 ns 3.3 ms 838.9 ms 1.2 Hz 305.1 Hz
φ/2 100 ns 6.5 ms 1.7 s 0.6 Hz 152.6 Hz
φ/4 200 ns 13.1 ms 3.4 s 0.3 Hz 76.3 Hz
φ/8 400 ns 26.2 ms 6.7 s 0.15 Hz 38.1 Hz
(3) 8-Bit Pulse Division Mode
PWM cycle = [16 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255)
PWM conversion cycle = [256 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255)
Table 8.5 Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20 MHz
(at 8-bit counter operation)
PWM Conversion Period Carrier Frequency (1/PWM cycle)
Internal Clock
Frequency
Resolution Min. Max. Min. Max.
φ 50 ns 12.8 μs 3.3ms 4482.8Hz 1250.0 kHz
φ/2 100 ns 25.6 μs 6.6ms 2441.4Hz 625.0 kHz
φ/4 200 ns 51.2 μs 13.1ms 1220.7Hz 312.5 kHz
φ/8 400 ns 102.4 μs 26.2ms 610.4Hz 156.3 kHz