Datasheet

Section 8 8-Bit PWM Timer (PWMU)
Rev. 3.00 Sep. 28, 2009 Page 213 of 910
REJ09B0350-0300
If the PWMREG value is changed during PWM output, the PWMREG value is loaded into
REGLAT when the duty counter overflows (at the beginning of the next PWM cycle). The
following shows the PWMU output waveform when the PWMREG value is changed.
H'FF
Duty counter
REGLAT
REGLAT'
(value after write)
H'00
PWMUO
PWMREG
write signal
Figure 8.6 PWMU Output Waveform When PWMREG Value is Changed
When the PWMPRE value is changed during PWM output, the PWM cycle changes from the next
cycle. When the clock generator counter underflows, the PWMPRE value is loaded into PRELAT.
The following shows the PRELAT update timing when the PWMPRE value is changed.
Clock generation counter
PRELAT
'
PRELAT
PRELAT
''
H'00
PWMPRE
write signal
PWMPRE
' PWMPRE ''
Figure 8.7 PRELAT Update Timing When PWMPRE Value is Changed