Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxv of xliv
REJ09B0350-0300
Item Page Revision (See Manual for Details)
25.2 Register Bits 807 Table amended
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
ADDRA
ADDRB
ADDRC
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
Bit 14
Bit 6
Bit 14
Bit 6
Bit 14
Bit 6
Bit 14
Bit 6
Bit 14
Bit 6
Bit 14
Bit 6
Bit 14
Bit 6
Bit 14
Bit 6
Bit 13
Bit 5
Bit 13
Bit 5
Bit 13
Bit 5
Bit 13
Bit 5
Bit 13
Bit 5
Bit 13
Bit 5
Bit 13
Bit 5
Bit 13
Bit 5
Bit 12
Bit 4
Bit 12
Bit 4
Bit 12
Bit 4
Bit 12
Bit 4
Bit 12
Bit 4
Bit 12
Bit 4
Bit 12
Bit 4
Bit 12
Bit 4
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 11
Bit 3
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 10
Bit 2
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
A/D
converter
25.3 Register States in Each
Operating Mode
822 Table amended
Register
Abbreviation
Module
Stop
Software
Standby
High-
Speed/Medium
speedReset Watch Sleep Module
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
ADDRA
ADDRB
ADDRC
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
A/D
converter
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
25.4 Register Selection
Condition
838 Table amended
Register
AbbreviationLower Address Register Selection Condition Module
ADDRA
ADDRB
ADDRC
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
H'FC00
H'FC02
H'FC04
H'FC06
H'FC08
H'FC0A
H'FC0C
H'FC0E
MSTP9 = 0 A/D converter