Datasheet

Section 9 14-Bit PWM Timer (PWMX)
Rev. 3.00 Sep. 28, 2009 Page 225 of 910
REJ09B0350-0300
9.3.4 Peripheral Clock Select Register (PCSR)
PCSR and the CKS bit of DACR select the operating speed.
Bit Bit Name
Initial
Value
R/W Description
7
6
⎯
⎯
0
0
R/W
R/W
Reserved
The initial value should not be changed.
5
4
PWCKXB
PWCKXA
0
0
R/W
R/W
PWMX clock select
These bits select a clock cycle with the CKS bit of
DACR of PWMX being 1.
See table 9.3.
3 to 1 ⎯ All 0 R/W Reserved
The initial value should not be changed.
0 PWCKXC 0 R/W PWMX clock select
This bit selects a clock cycle with the CKS bit of DACR
of PWMX being 1.
See table 9.3.
Table 9.3 Clock Select of PWMX
PWCKXC PWCKXB PWCKXA Resolution (T)
0 0 0 Operates on the system clock cycle (t
cyc
) x 2
0 0 1 Operates on the system clock cycle (t
cyc
) x 64
0 1 0 Operates on the system clock cycle (t
cyc
) x 128
0 1 1 Operates on the system clock cycle (t
cyc
) x 256
1 0 0 Operates on the system clock cycle (t
cyc
) x 1024
1 0 1 Operates on the system clock cycle (t
cyc
) x 4096
1 1 0 Operates on the system clock cycle (t
cyc
) x 16384
1 1 1 Setting prohibited