Datasheet

Section 9 14-Bit PWM Timer (PWMX)
Rev. 3.00 Sep. 28, 2009 Page 232 of 910
REJ09B0350-0300
t
f1
t
f2
t
f255
t
f256
t
L1
t
L2
t
L3
t
L255
t
L256
1 conversion cycle
t
f1
= t
f2
= t
f3
= ··· = t
f255
= t
f256
= T× 64
t
L1
+ t
L2
+ t
L3
+ ··· + t
L255
+ t
L256
= T
L
t
f1
t
f2
t
f63
t
f64
t
L1
t
L2
t
L3
t
L63
t
L64
1 conversion cycle
t
f1
= t
f2
= t
f3
= ··· = t
f63
= t
f64
= T× 256
t
L1
+ t
L2
+ t
L3
+ ··· + t
L63
+ t
L64
= T
L
(a) CFS = 0 [base cycle = resolution (T) × 64]
(b) CFS = 1 [base cycle = resolution (T) × 256]
Figure 9.4 Output Waveform (OS = 0, DADR corresponds to T
L
)