Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep. 28, 2009 Page 296 of 910
REJ09B0350-0300
(4) Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 10.42 shows the
timing for status flag clearing by the CPU.
T1 T2
TSR write cycle
TSR address
φ
Address
Write signal
Status flag
Interrupt
request signal
Figure 10.42 Timing for Status Flag Clearing by CPU