Datasheet

Section 12 16-Bit Duty Period Measurement Timer (TDP)
Rev. 3.00 Sep. 28, 2009 Page 333 of 910
REJ09B0350-0300
Channel Register Name Abbreviation R/W
Initial
Value
Address
Data
Bus
Width
TDP timer counter_2 TDPCNT_2 R/W H'0000 H'FB80 16
TDP pulse width upper limit
register_2
TDPWDMX_2 R/W H'FFFF H'FB82 16
TDP pulse width lower limit register_2 TDPWDMN_2 R/W H'0000 H'FB84 16
TDP cycle upper limit register_2 TDPPDMX_2 R/W H'FFFF H'FB86 16
TDP cycle lower limit register_2 TDPPDMN_2 R/W H'0000 H'FB90 16
TDP input capture register_2 TDPICR_2 R H'0000 H'FB88 16
TDP input capture buffer register_2 TDPICRF_2 R H'0000 H'FB8A 16
TDP status register_2 TDPCSR_2 R/W H'00 H'FB8C 8
TDP control register 1_2 TDPCR1_2 R/W H'00 H'FB8D 8
Channel 2
TDP control register 2_2 TDPCR2_2 R/W H'00 H'FB8F 8
TDP interrupt enable register_2 TDPIER_2 R/W H'00 H'FB8E 8
12.3.1 TDP Timer Counter (TDPCNT)
TDPCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to
CKS0 in TDPCR1. When CKS2 to CKS0 are set to B'111, the external clock is selected. Rising or
falling edge is selected by CKSEG in TDPCSR.
When TDPCNT overflows (H'FFFF changes to H'0000), the OVF flag in TDPCSR is set to 1. In
timer mode, TDPCNT is initialized to H'0000 when the CST bit in TDPCR1 is cleared. In cycle
measurement mode, TDPCNT is cleared when the first edge (the edge selected by the IEDG bit in
TDPCR1) of the measurement period (equal to one input waveform period) is detected.
In timer mode, TDPCNT is always writable. In cycle measurement mode, TDPCNT cannot be
modified. TDPCNT must always be accessed in 16-bit units and cannot be accessed in 8-bit units.
TDPCNT is initialized to H'0000.