Datasheet

Section 12 16-Bit Duty Period Measurement Timer (TDP)
Rev. 3.00 Sep. 28, 2009 Page 348 of 910
REJ09B0350-0300
Figure 12.8 shows an example of timing in cycle measurement.
H'0001H'0000 H'0001 N - 1 H'0000NM
TDPCNT
clear signal
TDPCNT
input clock
TDPCNT
N
M
M
1L
1
LK
φ
TDPCYI
TDPICR
TDPWDMX/TDPWDMN/
TDPPDMX/TDPPDMN
TDPICRF
Figure 12.8 Example of Timing in Cycle Measurement
When the PMMS bit in TDPCR2 is set to 1, cycle measurement is performed only while the
TDPMCI signal is high. Figure 12.9 shows an example of timing in cycle measurement when the
PMMS bit is set to 1.
φ
TDPCYI
TDPMCI
TDPCNT
H'0006M 012345670123456789AB01234
H'0003M H'0003 H'0007
H'000B
H'0005L
5
TDPICR
Figure 12.9 Example of Timing in Cycle Measurement (PMMS Bit = 1).