Datasheet

Section 13 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 377 of 910
REJ09B0350-0300
13.5.4 Timing of Counter Clear at Compare-Match
TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a
compare-match.
φ
N H'00
Compare-match
signal
TCNT
Figure 13.8 Timing of Counter Clear by Compare-Match
13.5.5 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
13.9 shows the timing of clearing the counter by an external reset input.
φ
Clear signal
External reset
input pin
TCNT N
H'00N – 1
Figure 13.9 Timing of Counter Clear by External Reset Input