Datasheet

Section 1 Overview
Rev. 3.00 Sep. 28, 2009 Page 3 of 910
REJ09B0350-0300
Classification
Module/
Function
Description
CPU MCU
operating
mode
Mode 2: Single-chip mode
(selected by driving the MD2 and MD0 pins low and MD1
pin high)
Mode 4: Boot mode
(selected by driving the MD2 high and MD1 and MD0 pins
low)
Mode 6: On-chip emulation mode
(selected by driving the MD2 and MD1 pins high and the
MD0 pin low)
Note: MD0 is not available as a pin and is internally fixed to 0.
• Power-down state (transition to the power-down state made by
the SLEEP instruction)
Interrupt
(source)
Interrupt
controller
• 41 external interrupt pins (NMI, IRQ15 to IRQ0 (ExIRQ15 to
ExIRQ6), KIN15 to KIN0, and WUE15 to WUE8)
• 63 internal interrupt sources
• Two interrupt control modes (specified by the system control
register)
• Two levels of interrupt priority orders specifiable (by setting the
interrupt control register)
• Independent vector addresses
Clock Clock pulse
generator
(CPG)
• Two clock generation circuits
• Clock pulse generator and subclock input circuit
System clock (φ) synchronization: 8 to 20 MHz
• Five power-down modes: Medium-speed mode, sleep mode,
watch mode, software standby mode, and module stop mode
A/D converter A/D
converter
(ADC)
• 10-bit resolution × 16 input channels
• Sample and hold function included
• Conversion time: 4 μs per channel (with A/D conversion clock
ADCLK at 10 MHz operation)
• Two operating modes: single mode and scan mode
• Three methods to start A/D conversion: software and two timer
(TPU/TMR) triggers