Datasheet

Section 17 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 503 of 910
REJ09B0350-0300
Section 17 I
2
C Bus Interface (IIC)
This LSI has a three-channel I
2
C bus interface. The I
2
C bus interface conforms to and provides a
subset of the Philips I
2
C bus (inter-IC bus) interface functions. The register configuration that
controls the I
2
C bus differs partly from the Philips configuration, however.
17.1 Features
• Selection of addressing format or non-addressing format
⎯ I
2
C bus format: addressing format with an acknowledge bit, for master/slave operation
⎯ Clocked synchronous serial format: non-addressing format without an acknowledge bit, for
master operation only
• Conforms to Philips I
2
C bus interface (I
2
C bus format)
• Two ways of setting slave address (I
2
C bus format)
• Start and stop conditions generated automatically in master mode (I
2
C bus format)
• Selection of the acknowledge output level in reception (I
2
C bus format)
• Automatic loading of an acknowledge bit in transmission (I
2
C bus format)
• Wait function in master mode (I
2
C bus format)
⎯ A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement.
⎯ The wait can be cleared by clearing the interrupt flag.
• Wait function (I
2
C bus format)
⎯ A wait request can be generated by driving the SCL pin low after data transfer.
⎯ The wait request is cleared when the next transfer becomes possible.
• Interrupt sources
⎯ Data transfer end (including when a transition to transmit mode with I
2
C bus format occurs,
when ICDR data is transferred from ICDRT to ICDRS or from ICDRS to ICDRR, or
during a wait state)
⎯ Address match: When any slave address matches or the general call address is received in
slave receive mode with I
2
C bus format (including address reception after loss of master
arbitration)
⎯ Arbitration lost
⎯ Start condition detection (in master mode)
⎯ Stop condition detection (in slave mode)
• Selection of 16 internal clocks (in master mode)