Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TFLGA 145 (9x9) 16-Bit 20 MHz I/O number 112

Section 17 I

2

C Bus Interface (IIC)

Rev. 3.00 Sep. 28, 2009 Page 505 of 910

REJ09B0350-0300

φ

SCL

ExSCLA

ExSCLB

PS

Noise

canceler

Bus state

decision

circuit

Arbitration

decision

circuit

Output data

control

circuit

ICCR

Clock

control

ICXR

ICMR

ICSR

ICDRS

Address

comparator

SAR, SARX

SDA

Noise

canceler

Interrupt

generator

Interrupt

request

Internal data bus

ICDRR

ICDRT

[Legend]

ICCR:

ICMR:

ICSR:

ICDR:

ICXR:

SAR:

SARX:

PS:

Note : * An input/output pin can be selected among three pins (IIC_0 and IIC_1).

I

2

C bus control register

I

2

C bus mode register

I

2

C bus status register

I

2

C bus data register

I

2

C bus extended control register

Slave address register

Slave address register X

Prescaler

ExSDAA

ExSDAB

*

*

Figure 17.1 Block Diagram of I

2

C Bus Interface