Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 603 of 910
REJ09B0350-0300
R/W
Bit Bit Name
Initial
Value
Slave Host Description
1 IBFIE1 0 R/W ⎯ IDR1 Receive Complete interrupt Enable
Enables or disables IBFI1 interrupt to the slave (this
LSI).
0: Input data register (IDR1) receive complete
interrupt requests disabled
1: Input data register (IDR1) receive complete
interrupt requests enabled
0 ERRIE 0 R/W ⎯ Error Interrupt Enable
Enables or disables ERRI interrupt to the slave (this
LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
Note: * Only 0 can be written to bits 6 to 4, to clear the flag.
• HICR3
R/W
Bit Bit Name Initial Value Slave Host Description
7 LFRAME Undefined R ⎯ LFRAME Pin Monitor
6 CLKRUN Undefined R ⎯ CLKRUN Pin Monitor
5 SERIRQ Undefined R ⎯ SERIRQ Pin Monitor
4 LRESET Undefined R ⎯ LRESET Pin Monitor
3 LPCPD Undefined R ⎯ LPCPD Pin Monitor
2 PME Undefined R ⎯ PME Pin Monitor
1 LSMI Undefined R ⎯ LSMI Pin Monitor
0 LSCI Undefined R ⎯ LSCI Pin Monitor