Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 604 of 910
REJ09B0350-0300
19.3.3 Host Interface Control Register 4 (HICR4)
HICR4 enables/disables channel 4 and controls interrupts to the channel 4 of an LPC interface
slave (this LSI).
R/W
Bit Bit Name
Initial
Value Slave Host Description
7 ⎯ 0 R/W ⎯ Reserved
The initial value bit should not be changed.
6 LPC4E 0 R/W ⎯ LPC Enable 4
0: LPC channel 4 is disabled
For IDR4, ODR4, and STR4, address (LADR4)
match is not occurred.
1: LPC channel 4 enabled
5 IBFIE4 0 R/W ⎯ IDR4 Receive Completion Interrupt Enable
Enables or disables IBFI4 interrupt to the slave (this
LSI).
0: Input data register (IDR4) receive complete
interrupt requests disabled
1: Input data register (IDR4) receive complete
interrupt requests enabled
4 to 0 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be changed.