Datasheet

Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 615 of 910
REJ09B0350-0300
• STR2
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
DBU27
DBU26
DBU25
DBU24
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
Defined by User
The user can use these bits as necessary.
3 C/D2 0 R R Command/Data
When the host writes to IDR2, bit 2 of the I/O
address is written into this bit to indicate whether
IDR2 contains data or a command.
0: Content of input data register (IDR2) is a data
1: Content of input data register (IDR2) is a
command
2 DBU22 0 R/W R Defined by User
The user can use this bit as necessary.
1 IBF2 0 R R Input Buffer Full
This bit is an internal interrupt source to the slave
(this LSI).
0: [Clearing condition]
When the slave reads IDR2
1: [Setting condition]
When the host writes to IDR2 in I/O write cycle
0 OBF2 0 R/(W)* R Output Buffer Full
0: [Clearing conditions]
• When the host reads ODR2 in I/O read cycle
• When the slave writes 0 to the OBF2 bit
1: [Setting condition]
When the slave writes to ODR2
Note: * Only 0 can be written to clear the flag.