Datasheet

Section 22 Flash Memory
Rev. 3.00 Sep. 28, 2009 Page 714 of 910
REJ09B0350-0300
One erasure processing erases one block. For details on block divisions, refer to figure 22.4. To
erase two or more blocks, update the erase block number and repeat the erasing processing for
each block.
1. Select the on-chip program to be downloaded and the download destination. When the PPVS
bit in FPCS is set to 1, the programming program is selected. Several programming/erasing
programs cannot be selected at one time. If several programs are selected, a download error is
returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download
destination is specified by FTDAR.
For the procedures to be carried out after setting FKEY, see section 22.8.2 (2), Programming
Procedure in User Program Mode.
2. Set the FEBS parameter necessary for erasure. Set the erase block number (FEBS parameter)
of the user MAT in general register ER0. If a value other than an erase block number of the
user MAT is set, no block is erased even though the erasing program is executed, and an error
is returned to the FPFR parameter.
3. Erasure is executed. Similar to as in programming, the entry point of the erasing program is at
the address which is 16 bytes after #DLTOP (start address of the download destination
specified by FTDAR). Call the subroutine to execute erasure by using the following steps.
MOV.L #DLTOP+16, ER2 ; Set entry address to ER2
JSR @ER2 ; Call erasing routine
NOP
• The general registers other than R0L are held in the erasing program.
• R0L is a return value of the FPFR parameter.
• Since the stack area is used in the erasing program, a stack area of 128 bytes at the
maximum must be allocated in RAM.
4. The return value in the erasing program, the FPFR parameter is determined.
5. Determine whether erasure of the necessary blocks has finished. If more than one block is to
be erased, update the FEBS parameter and repeat steps 2 to 5.
6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by
a reset immediately after erasure has finished, secure the reset input period (period of RES = 0)
of at least 100 μs.