Datasheet

Section 23 Clock Pulse Generator
Rev. 3.00 Sep. 28, 2009 Page 763 of 910
REJ09B0350-0300
Table 23.4 External Clock Output Stabilization Delay Time
Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V
Item Symbol Min. Max. Unit Remarks
External clock output stabilization delay
time
t
DEXT
* 500 ⎯ μs Figure 23.6
Note: * t
DEXT
includes a RES pulse width (t
RESW
).
t
DEXT
*
RES
(Internal and external)
EXTAL
V
CC
3.0 V
φ
Note: * The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW).
Figure 23.6 Timing of External Clock Output Stabilization Delay Time